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100G UDP IP Stack

Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs

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ApSRAM Controller (will not be supported for FPGA devices, can be used during SoC Protyping in FPGA)

ApSRAM Controller is a low-latency, low-power IP scalable from 64Mb to 1Gb with multi-bank architecture for high throughput. Designed for AI/ML, edge, automotive, and IoT systems, it supports AXI interface and various silicon technologies. It simplifies SRAM replacement while ensuring compliance and interoperability.

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ARINC 429 IP Core

Logic Fruit's ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps.

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ARINC 818 IP CORE

ARINC 818 (ADVB) is a high data rate video bus based on the ANSI Fiber Channel Audio-Video (FC-AV) protocol standards. Emphasizing cost reduction as well as speeding up the link initialization. ARINC 818 is a unidirectional interface that was developed for avionics systems, such as connecting mission processors to cockpit displays like HUDS, MFDs, PFDs, or HMDs. Used widely in Boeing 787 and the KC46A tanker, Airbus A350 and A400M, the COMAC C-919, the C-17, F15, F18 and various military aircrafts.

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CXL 3 CONTROLLER IP

The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems. It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer. Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.

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DDR5/4 and LPDDR3/2 Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s UMMC supports DDR5/4/3, LPDDR3/2, RLDRAM2/3, and 3DS memory interfaces for mobile, consumer, and networking applications. It provides high-bandwidth, low-power access with dynamic power management and high-frequency operation. The controller supports rapid debug and seamless SoC integration.

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DISPLAY PORT IPs

Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.

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Enterprise Flash Controller - ONFI/Toggle (Silicon Proven IP for Altera Devices)

Mobiveil’s ONFI/Toggle NAND Controller is designed for enterprise SSDs, supporting ONFI 5.2 and Toggle NAND protocols. It enables high-speed multi-page data transactions with optional LDPC support for enhanced reliability. Its flexible addressing and pipeline performance make it ideal for next-gen flash systems.

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JESD204B TRANSMITTER AND RECEIVER IP

Logic Fruit's JESD204B RTL IP supports increased lane rates up to 12.5Gbps for higher bandwidth applications. It can be configured to transmit or receive using a 8B10B link layer to achieve deterministic latency, SerDes synchronization, clock recovery and DC balance.

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Listing 9 out of 16 Offerings