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100G UDP IP Stack

Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs

10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

10GEDEK (10Gbits/s Ethernet Data Exchange Kit) IP Core

10G Ethernet processor-less stack

ARINC 429 IP Core

Logic Fruit's ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps.

ARINC 818 IP CORE

ARINC 818 (ADVB) is a high data rate video bus based on the ANSI Fiber Channel Audio-Video (FC-AV) protocol standards. Emphasizing cost reduction as well as speeding up the link initialization. ARINC 818 is a unidirectional interface that was developed for avionics systems, such as connecting mission processors to cockpit displays like HUDS, MFDs, PFDs, or HMDs. Used widely in Boeing 787 and the KC46A tanker, Airbus A350 and A400M, the COMAC C-919, the C-17, F15, F18 and various military aircrafts.

ChevinID

ChevinID is a silicon‑rooted authentication and protection solution designed to secure FPGA, ASIC, and embedded systems across the entire lifecycle. Built on Physically Unclonable Function (PUF) technology, ChevinID assigns each device a unique, intrinsic identity that cannot be copied or transferred, enabling strong, hardware‑level trust without external secure elements. The solution protects valuable intellectual property—including FPGA bitstreams, RTL designs, and embedded software—by binding execution and access to authenticated hardware. Cryptographic keys are securely contained within encrypted envelopes, ensuring they are never exposed during operation. This approach safeguards against cloning, reverse engineering, and unauthorized deployment. ChevinID also enables flexible, hardware‑based licensing models, allowing vendors to control feature activation, enforce usage policies, and create new revenue streams. For Intel/Altera FPGA users, ChevinID integrates seamlessly with exist

DISPLAY PORT IPs

Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.

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IntelliProp SATA AHCI Host Core (IPC-SA156A-HI)

IntelliProp SATA AHCI Host Core (IPC-SA156A-HI) is a highly reliable, silicon-proven Intellectual Property (IP) solution providing standard 6 Gb/s Serial-ATA (SATA 3.3) host connectivity. Optimized for Altera FPGAs, it enables rapid deployment of cost-effective, high-throughput storage solutions compliant with the widely supported AHCI register specification.

JESD204B TRANSMITTER AND RECEIVER IP

Logic Fruit's JESD204B RTL IP supports increased lane rates up to 12.5Gbps for higher bandwidth applications. It can be configured to transmit or receive using a 8B10B link layer to achieve deterministic latency, SerDes synchronization, clock recovery and DC balance.