Altera FPGAs Built for the RAN
The Radio Access Network (RAN) is rapidly evolving with the emergence of 6G, AI-driven optimizations, and increasingly diverse global standards. As demand grows for intelligent, differentiated wireless solutions, Altera FPGAs are purpose-built to meet these challenges—delivering the performance, power efficiency, and flexibility required for next-generation RAN architectures. With optimized silicon and tools, production-ready IPs and comprehensive O-RU Enablement Packages, Altera empowers customers to accelerate time to market and tailor AI-enhanced solutions for specific geographies, operators, and deployment models.
Why FPGAs
Flexibility for Evolving Standards
FPGAs are inherently reprogrammable, enabling rapid adaptation to new wireless standards—whether it’s shifting functional splits, protocol updates, or fresh spectrum allocations. Stay ahead of change without redesigning your hardware.
Power and Performance Efficiency
Built on advanced nodes with Hyperflex™ architecture, Altera FPGAs deliver industry-leading performance per watt—enabling real-time signal processing, high throughput, and lower OPEX without sacrificing flexibility or upgradeability.
Custom Intelligence, Beamforming, and Differentiation
Embed AI/ML inference, advanced beamforming, proprietary signal processing, or unique algorithms directly into your design. With Altera production O-RAN IP library and AI/ML example designs, you can deliver tailored, differentiated features—and get to market faster.
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Applications
6G AI RAN
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O-RAN RU Macro & Micro
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mMIMO Radio Units
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vRAN / Fronthaul
View Details ›6G AI RAN
AI CSI Compression: AI compresses channel state information, reducing fronthaul bandwidth up to 10× while preserving accuracy. Essential for scalable RAN deployments and lower transport costs. This compression algorithm can be taken and modified for many compression use cases.
AI CSI Compression: AI compresses channel state information, reducing fronthaul bandwidth up to 10× while preserving accuracy. Essential for scalable RAN deployments and lower transport costs. This compression algorithm can be taken and modified for many compression use cases.
AI Digital Pre-Distortion: AI-enhanced digital pre-distortion improves power amplifier efficiency and linearity, reducing power draw and thermal load in radio systems. In systems with power amplifiers, DPD accuracy can dramatically decrease OPEX.
AI Channel Estimation: Improves channel estimation accuracy for better spectral efficiency and link reliability in wireless PHY systems. Useful for ORAN and custom 5G/6G radio stacks. Through using an optimized DSP Builder AI implementation, we dramatically reduce DSP blocks by 67% and M20k utilization by 58% while maintaining the same throughput as traditional implementations.
Key Benefits
- Scalable, validated AI reference designs for early 6G development
- Continuous FPGA-based optimization as 6G standards evolve
- Production-grade LDPC IP enabling flexible, high-performance implementations
O-RAN RU Macro & Micro
Altera’s Sail River Enablement Package is built on production grade IP to provide a 4T4R example design. Built on our radio specific Agilex 7 Single F-tile SKU, this ADC/DAC vendor agnostic design is optimized for low cost, power efficient, and high throughput telco deployments.
Sail River is built to support openness, adhering to O-RAN and 3GPP standards. It delivers proven, integrated IP functions that are scalable and adaptable to customer-specific requirements.
Our supporting mechanical design features a robust 3-layer structure with an integrated cavity filter, ensuring durability, precision, and optimal performance.
Key Benefits
- Extremely modular to fit a broad variety of use-cases
- Easy to license and modify design to meet made in country requirements
- Validated with Keysight’s O-RAN Studio
FPGA Production Grade IP
mMIMO Radio Units
Altera’s Olympia Bridge mMIMO Enablement Package delivers a 32T32R example built on production-grade IP. This ADC/DAC vendor-agnostic design supports high utilization with minimal performance trade-offs, enabling scalable, power-efficient, and high-throughput mMIMO telco deployments.
Olympia Bridge is built to support openness, adhering to O-RAN and 3GPP standards. Powered by Agilex, it delivers a highly optimized beamforming compute block with proven IP that is scalable and adaptable to customer-specific requirements.
Olympia Bridge offers a flexible mechanical and development platform for mMIMO O-RUs, supporting PCB sources and BSP for rapid prototyping. With multiple licensing options, it enables IP development, validation, and demonstration from O-RAN LLS 7.2A through 7.2C, including user IP and application software.
Key Benefits
- Extremely modular to fit a broad variety of use-cases
- Easy to license and modify design to meet made in country requirements
- Validated with O-RAN Studio
FPGA Production Grade IP
vRAN / Fronthaul
Altera’s N6000 vRAN package delivers integrated xHAUL connectivity, LDPC FEC acceleration, and precision 1588 timing. Supporting Split 7-2x, virtualization, and optimized power, it accelerates high-performance, scalable 5G deployments.
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Altera’s Fronthaul Gateway Enablement Package simplifies multi-vendor interoperability across network generations (4G/5G) with modular IP, integrated switching, and 1588 timing support. Its flexible architecture is designed to smoothly evolve toward future 6G deployments.
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Key Benefits
- Accelerated FPGA processing reduces CPU load, enabling efficient vRAN and Fronthaul deployments
- Modular, interoperable IP simplifies multi-vendor 4G/5G integration with smooth upgrade paths to 6G
- Validated, scalable solutions significantly reduce OPEX/CAPEX and accelerate time-to-market
Customer Success Stories
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At Viavi, we've experienced firsthand the superior performance of Altera's AgilexTM 7 M-series FPGA. The Agilex 7 transceiver capability to implement both PAM4 and NRZ modulation within the same transceiver and achieve data rates up to 64G has been a game-changer. Agilex 7 M-series FPGA is also capable of supporting DDR5 and HBM2E memories that addresses the memory bandwidth in our design. These versatilities have enabled us to develop PCle testers more efficiently. With the Agilex 7 FPGA, we've significantly reduced our time to market to deliver lead-edge PCle protocol tester equipment. The technical support from the Altera team has allowed us to stay ahead in the fast-paced world of technology testing
Paul Mercer, SVP R&D, Viavi Solutions - Network System Enablement