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O-RAN FPGA IP

Altera

The O-RAN IP provides delay management service to ensure that it receives correct data over the fronthaul interface despite packet delay variation (PDV). The IP refers to concept and latency models from the eCPRI specification. The IP manages transmission and receiver windows, which you can place relative to the air interface based on predefined or measured transport delay. The IP exchanges RU parameters and network characteristic over M-plane messages. The IP monitors and counts packets transmitted or received out of the window to warn the other node and discard them if necessary. The IP also transmits and receives non-delay managed U-plane traffic for which normal windows are not applicable.

Key Features

  • Support for CAT-A RU (up to 8 spatial streams)
  • Support for CAT-B RU (precoding in RU)
  • Support for section extensions from 1 to 11
  • Transmission blanking energy savings
  • Preconfigured transport delay method CU–RU timing
  • Section type 0, type 1, and type 3
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Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Development Language Verilog, VHDL

Encrypted Verilog source code

Design Example

Simulation Models

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

Market Segment and Sub-Segments