Nios® V processors are the next generation of soft processor IPs, designed to bring the power and flexibility of the open-source RISC-V Architecture to FPGA environments. By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

Altera
Key Features
- Leverage the power of the open source RISC-V community-maintained ecosystem to expedite your path to market.
- Select from modern toolchains, debuggers, and real-time operating systems (RTOS) available from the RISC-V ecosystem, for your software development.
- Debug your design with the supported Joint Test Action Group (JTAG) debug module, offering on-chip debugging capabilitie, Simple and Standard Flows with Easy System Integration
- Utilize traditional hardware tool flows, such as Platform Designer and the Quartus® Prime Software to build a design from scratch using the Nios V processor or migrate existing Nios II designs
- Meet high-performance levels and unparalleled flexibility for your embedded design with the Nios V processors.
- Eliminate the need for excessive expenses on high clock frequencies and power-hungry off-the-shelf processors.
- Seamlessly integrate CPUs, peripherals, memory interfaces, and custom peripherals within the Quartus Prime software.



Offering Brief
Offering Brief
Device Family | Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, MAX® V CPLD, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA |
---|---|
Offering Status | Production |
Integrated Testbench | No |
Evaluation License | No |
Design Examples Available | Yes |
Demo | No |
Compliance | No |
Development Language | Encrypted Verilog |
Encrypted Verilog source code
Design Examples
Documentation: Reference Manual, Embedded Processor Design Handbook, Ashling RiscFree IDE User Guide, Processor Migration Guidelines Application Note, Nios V Software Developer Handbook, Nios V Processor Lockstep Implementation User Guide, White Papers
Ordering Information
IP-NIOSVC, IP-NIOSVM, IP-NIOSVG
from Direct
Documentation & Resources
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