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FIR II FPGA IP Core

The FIR II IP cores provide a fully-integrated finite impulse response (FIR) filter function optimized for use with Altera FPGA devices.

MIPI D-PHY IP

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.