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Data Center

Powering Next-Generation Data Centers with FPGA Acceleration

FPGAs have become a cornerstone of modern, heterogeneous data center architectures, serving three critical functions across the infrastructure. 

First, High-Performance FPGAs drive the DPU and AI NIC segment, offloading compute-intensive protocols like RDMA, OVS (Open vSwitch), and security acceleration to achieve ultra-low, deterministic latency. Second, Storage Acceleration expands on this capability by offloading NVMe-oF protocols, real-time encryption/decryption, and hardware-based compression/decompression, significantly boosting throughput and TCO efficiency in massive storage clusters. Finally, Small-Form-Factor CPLDs provide essential Platform Management and Security, governing power sequencing, I/O expansion, and the hardware Root of Trust (RoT) to ensure system-level resilience and firmware integrity. Together, these tiers enable a highly efficient, scalable, and secure infrastructure capable of handling next-generation AI and cloud workloads. 

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Why Altera FPGAs

High-Performance, Ultra-Low Latency Processing

FPGAs avoid CPU overhead by using parallel hardware pipelines, delivering deterministic ultra-low latency and wire-speed throughput for high-bandwidth tasks like RDMA and OVS—eliminating the “CPU tax” in AI and storage networks.

Architectural Flexibility & Future-Proofing

FPGAs provide a “Hardware-as-Code” advantage, letting you reprogram DPUs for new AI models or standards like PQC and CXL—avoiding hardware obsolescence and enabling software-speed innovation with hardware efficiency.

IO Versatility & “Standard Agility”

FPGAs and CPLDs serve as “universal glue” on server boards, bridging legacy and modern protocols while handling power and security logic—enabling flexible designs that adapt to new standards without costly PCB redesigns.

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Agilex™ 7

Agilex™ 5

Applications

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DPU & AI NIC

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Storage

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Platform Management

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AI Inference

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Modern data centers are strained by exploding data growth, AI-driven workloads, and the rising cost of CPU-based storage processing. Traditional architectures struggle with NVMe‑oF protocol overhead, inline encryption/compression latency, and inconsistent tail performance. FPGA-based storage acceleration solves these bottlenecks by moving critical data services—protocol handling, data reduction, cryptography, metadata operations—into a deterministic, line‑rate hardware pipeline. This enables predictable low latency, improved throughput-per-watt, and a flexible, future-proof storage architecture that scales with modern AI, analytics, and cloud workloads.

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Three Key Sections of Storage Acceleration 

1. Front-End Fabric Acceleration 

FPGA acceleration offloads storage networking functions such as NVMe‑oF (TCP/RoCE), RDMA, queue steering, checksum, and packet processing, delivering deterministic line‑rate performance and freeing host CPUs for application logic. 

2. Inline Data Services & Computational Storage 

FPGA-based pipelines perform latency-sensitive operations—compression, encryption, hashing, erasure coding, metadata filtering, and data reduction—directly in the I/O path, reducing CPU load and improving efficiency for AI and analytics workflows. 

3. Backend Storage Processing & Array Offload 

FPGAs accelerate backend services such as RAID, replication, journaling, block mapping, and SSD management. This enables higher sustained throughput, consistent tail latency, and scalable performance for all-flash arrays and disaggregated storage architectures. 

Platform Management is required wherever a system’s hardware needs to be overseen and supervised, such as a server platform, an accelerator module, and add-in card, just to name a few. Platform management embraces everything from low-end tasks such as power-sequencing when the system is powered-on or powered-off, which may be implemented by using CPLDs or entry-level FPGAs, all the way to high-end activities such as resource discovery, telemetry, configuraiton, control, update, security, and resiliency, which may require specialized Baseboard Management Controller (BMC) devices. 

Altera FPGAs, such as MAX10, Agilex 3, and Agilex 5, are optimized to perform the platform management functions from Host Processor Module (HPM), SCM (Secure Control Module), and PRoT (Platform Root of Trust) to BMC. The platform management solution using Altera FPGAs provides great flexibility and scalability, faster Time-to-Market (TTM), and lower Total Cost of Ownership (TCO).  

The flexibility and scalability of the Altera FPGA-based solution provide customers with the possibility to address the evolving security standards and protocols. Faster enabling and TTM make it possible to achieve Best-in-Class security, in-field upgradability, ease of scaling up or down for various platform architectures/generations, and no legacy burden. Customers can also benefit from a lower TCO through competitive BOM, board area, and consolidated functions into one FPGA. The Intel 7 technology based Agilex FPGA also ensures better processor and supply resilience. 

Altera is an advocate for Open Source and OCP (Open Compute Project) as an active participant in OCP and OpenBMC. 

The diagram below indicates all the platform management components and their functions. 

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The FlexBMC FPGA in the green-dash-square can be implemented on a single Agilex 5 FPGA that can perform BMC, SCM and PRoT functions, which provides a lot of benefits for customers.