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100 Gbit/s IEEE 802.3bj RS Encoder/ Decoder
The Creonic IP cores are the ideal solution for throughputs beyond 10 Gbit/s for FPGA devices and throughputs of up to 100 Gbit/s on state-of-the-art ASIC technologies.
By Creonic GmbH
100G UDP IP Stack
Logic Fruit’s 100G UDP IP Stack – Optimized for high-speed 100G data transfer with minimal CPU dependency. Fully supports ARP and ICMP for reliable network connectivity and easy integration into SoC designs
By Logic Fruit Global Technologies Inc
4G LTE/LTE-A CTC
Creonic’s LTE/LTE-A IP core is an advanced, customer proven implementation of the standardized 3GPP turbo code.
By Creonic GmbH
5G LDPC-V FPGA IP
Low-density parity-check (LDPC) IP helps transmit and receive messages over noisy channels. This IP implements LDPC codes compliant with the 3rd generation partnership project 5G specification.
By Altera
AES - Advanced Encryption Standard Engine
The AES encryption IP core implements hardware Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES-S) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES-F) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. Various cipher modes can be supported (CBC, CFB, CTR, ECB, LRW, and OFB). The core works with a pre-expanded key, or with optional key expansion logic. The AES core is a fully synchronous design and has been evaluated in a variety of technologies. It is available optimized for ASICs or FPGAs, with complete deliverables.
By Computer Aided Software Technologies, Inc (dba CAST)
ARINC 429 IP Core
Logic Fruit's ARINC 429 IP Core is a multichannel module with support for virtually any number of transmitters and Receivers. Both low speed (12.5 Kbps) and high speed (100 Kbps) data rates are supported for data transmission, along with other configurable data rates from 12.5 Kbps to 1 Mbps.
By Logic Fruit Global Technologies Inc
ASCON-F: ASCON Authenticated Encryption & Hashing Engine
The ASCON-F IP is a compact, high-throughput HW core implementing the lightweight authenticated encryption with associated data (AEAD) & hashing algorithms of the Ascon v1.2 spec. A single instance supports encryption & decryption with Ascon-128 & Ascon-128a, as well as cryptographic hashing with Ascon-Hash & Ascon-Hasha. Operation mode, key, and nonce values are run-time programmable & can change per input block. The core provides simple I/O I/F, optionally bridged to AXI4-Stream or AXI4 Memory Mapped ports through CAST bridges. It synthesizes to ~11k gates & runs at over 2GHz in modern ASIC technologies. Excluding padding & initialization, throughput ranges from 5.3 to 16 bits/cycle, or 10.6 to 32Gbps at 2GHz, with higher throughput possible by instantiating multiple cores. Easy to use & integrate, following best coding & verification practices, has no multi-cycle or false paths, uses only rising-edge D flip-flops, no tri-states or SRAMs, and operates in a single clock/reset domain.
By Computer Aided Software Technologies, Inc (dba CAST)
ATSC 8-VSB Modulator
The CMS0033 ATSC 8-VSB modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
By Commsonic Ltd
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP core supports the LDPC coding schemes and is an ideal fit for further applications with highest demands on forward error correction.
By Creonic GmbH