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Video and Image Processing
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1G-100G Robo/TSN Industrial Network Virtualization and Acceleration for Converged OT/IT - MLE FPGA Design Services

Openness has greatly benefited other industries like automotive, aerospace, banking, datacenters, and finally OT: No vendor lock-in, higher flexibility and better long-term-availability. Cost reduction for Overall Equipment Effectiveness (OEE). Meets today’s cyber security requirements. Opens-up use of AI.

3D LUT Altera® FPGA IP

The 3D Look-Up Table (LUT) Altera® FPGA IP, part of the Video and Vision Processing (VVP) Suite, delivers a high-performance, resource-efficient solution for video color space conversion, dynamic range adjustment, chroma keying, and artistic effect generation, enabling superior image quality in broadcast and professional video applications.

BxBChan Channelizer

An efficient implementation of a Polyphase Filter Bank channelizer.

BxBFFT Fast Fourier Transform

An extraordinarily Fast, Efficient, and Feature-Packed FFT implementation.

DISPLAY PORT IPs

Logic Fruit's Display Port Transmitter & Receiver IP Cores support multiple line rates up to 8.1 Gbps. The IP cores have been developed as per Display Port specifications DP2.0/eDP1.5.

H.264 Baseline, Main and High Profiles Single- and Multi-channel Encoder IP Core

The H264-HP-E core from Alma Technologies is an advanced and self-contained ITU-T H.264 High profiles hardware encoder.

H264-E-BPF - Ultra-fast, AVC/H.264 Baseline Profile Encoder

The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The H264-E-BPF encoder requires less silicon area than most equally capable hardware H.264 encoders—approximately 250K gates—allowing for very cost-effective implementations. Its small silicon footprint, low external memory bandwidth requirements, and zero software overhead enable high-throughput H.264 coding at an extremely low energy cost.

HDMI IP Core

The HDMI Altera® FPGA IP core delivers high-performance, standards-compliant support for the latest HDMI specifications, enabling seamless transmission of high-definition audio and video over a single interface. It provides a robust and flexible solution for integrating next-generation video display connectivity into Altera FPGA designs.

High Dynamic Range (HDR) IP - using single exposure

Real-time, high-quality HDR IP with virtually zero latency, based on a single exposure. The IP is designed for FPGAs and can be embedded seamlessly in Gidel’s modular vision/imaging grabbing and image processing systems, which include PCIe boards and edge computers supporting GigE Vision, CoaXPress, Camera Link, and user-defined protocols.