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Compute Express Link (CXL)
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10GBASE-R PHY FPGA IP

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

Altera® FPGA Design Services / IP Design Services - MLE

MLE offers FPGA design services for Altera® FPGAs, which give a wide variety of configurable embedded SRAM, high-speed transceivers, high-speed I/Os, logic blocks, and routing. Built-in intellectual property (IP) combined with outstanding software tools lower FPGA development time, power, and cost.

Compute Express Link (CXL) IP

CXL IP is designed to provide the added memory bandwidth and capacity, and acceleration needed for a wide range of data-intensive workloads.

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Current: xSPI Initiator core.  

xSPI Memory Controller Core for PSRAM, NOR Flash, STT-MRAM. Protocols: (a) JEDEC xSPI Profile 1.0, 2.0; (b) HyperBus 1.0, 2.0, 3.0; (c) OctaBus; (d) Octal Bus; (e) Exccela Bus. SLL support x8 and x16 PSRAM devices, and support chaining two x16 PSRAM devices to create x32 PSRAM channel.

CXL 3 CONTROLLER IP

The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for advanced systems. It supports multiple channels and configurable CXL degraded modes, ensuring seamless integration with CXL devices and enabling high-performance data transfer. Ideal for versatile system designs, it accommodates all three CXL device types to facilitate efficient connectivity and scalable architecture.

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IntelliProp SATA AHCI Host Core (IPC-SA156A-HI)

IntelliProp SATA AHCI Host Core (IPC-SA156A-HI) is a highly reliable, silicon-proven Intellectual Property (IP) solution providing standard 6 Gb/s Serial-ATA (SATA 3.3) host connectivity. Optimized for Altera FPGAs, it enables rapid deployment of cost-effective, high-throughput storage solutions compliant with the widely supported AHCI register specification.