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5G LDCPC-V FPGA IP

Altera

Low-density parity-check (LDPC) codes are linear error correcting codes that help you to transmit and receive messages over noisy channels. The 5G LDPC and LDPC-V FPGA IP implement LDPC codes compliant with the 3rd Generation Partnership Project (3GPP) 5G specification for integration in your wireless design. LDPC codes offer better spectral efficiency than Turbo codes and support the high throughput for 5G new radio (NR).

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Key Features

  • DOCSIS 3.1 Support: Decoder, On-the-fly switching between code
  • WiMedia 1.5 Support: Encoder/Decoder, variable code-word length, optional on-the-fly switching between code, support short and long frame
  • DVB-S2 encoder
  • NASA: Encoder/Decoder (CCSDS compliant), optional low resource architecture available, MSA or layered MSA decoding
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog, Encrypted VHDL

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, IP Release Notes

Ordering Information

IP-LDPCV

from Digikey

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IP-LDPCV

from Mouser

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Market Segment and Sub-Segments

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Wireless

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Wireless

5G/ 6G Radio

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