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eCPRI FPGA IP

Altera

The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0. It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.

Key Features

  • Compliant with the eCPRI Specification V2.0 (2018-06-25) available on the CPRI Industry Initiative (CII) website.
  • Supports eCPRI radio equipment controller (eREC) and eCPRI radio equipment (eRE) module configurations.
  • Supports Ethernet headers in a variety of formats, including VLAN tag, source/destination MAC address, IPv4, UDP extraction and encapsulation.
  • Supports eCPRI one-way delay measurement based on IEEE Standard 1588 Precision Time Protocol (1588 PTP) hardware timestamp.
  • Supports 25 Gbps and 10 Gbps Ethernet ports.
  • Supports pairing of eCPRI Altera® FPGA IP with O-RAN Altera® FPGA IP.
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available No
Demo No
Compliance No
Development Language Verilog, VHDL

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

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