Device Configuration Support Center

Device Configuration Support Center provides documentation and training to select a design, and implement configuration features.

1. Device Specific Configuration Details 2. Configuration Schemes and IP 3. Advanced Configuration Features 4. Quartus® Prime Software Design Flow 5. Board Design 6. Debug Supported Flash Memory Devices (Configuration Devices) Design Examples and Reference Designs Training Courses and Videos

The Device Configuration Support Center provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.

You will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.

Get additional support for Agilex™ 7 System Architecture, Agilex™ 5 System Architecture and the Agilex™ 3 System Architecture, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

1. Device Specific Configuration Details

Table 1 - Configuration Schemes and Features Overview

Device Family	Configuration Schemes					Configuration Features
	Scheme	Data Width	Max Clock Rate	Max Data Rate	Configuration Via Protocol	Design Security	Partial Reconfiguration ⁽²⁾	Decompression Support	Remote System Update	Single Event Upset
Agilex™ 7	Avalon® Streaming	32 bits	125 MHz	4000 Mbps	N/A	√	√	√	Parallel Flash Loader II IP core	√
		16 bits	125 MHz	2000 Mbps		√	√
		8 bits	125 MHz	1000 Mbps		√	√
	Active Serial (AS)	4 bits	166⁽¹⁾ MHz	664 Mbps	√	√	√		√	√
	JTAG	1 bit	30 MHz	30 Mbps	N/A	√	√		N/A	√
Agilex™ 5	Avalon® Streaming	16 bits	125 MHz	2000 Mbps	N/A	√	√	√	Parallel Flash Loader II IP core	√
	Avalon® Streaming	8 bits	125 MHz	1000 Mbps	N/A	√	√		Parallel Flash Loader II IP core	√
	Active Serial (AS)	4 bits	166⁽¹⁾ MHz	664 Mbps	√	√	√		√	√
	JTAG	1 bit	30 MHz	30 Mbps	N/A	√	√		N/A	√
Agilex™ 3	Avalon® Streaming	16 bits	125 MHz	2000 Mbps	N/A	√	√	√	Parallel Flash Loader II IP core	√
	Avalon® Streaming	8 bits	125 MHz	1000 Mbps	N/A	√	√		Parallel Flash Loader II IP core	√
	Active Serial (AS)	4 bits	166⁽¹⁾ MHz	664 Mbps	√	√	√		√	√
	JTAG	1 bit	30 MHz	30 Mbps	N/A	√	√		N/A	√
Stratix® 10	Avalon®-ST	32 bits	125 MHz	4000 Mbps	N/A	√	√	√	Parallel Flash Loader II IP core	√
		16 bits	125 MHz	2000 Mbps		√	√
		8 bits	125 MHz	1000 Mbps		√	√
	Active Serial (AS)	4 bits	125⁽¹⁾MHz	500 Mbps	√	√	√		√	√
	JTAG	1 bit	30 MHz	30 Mbps	N/A	√	√		N/A	√
Arria® 10	Configuration via HPS	32 bits	100 MHz	3200 Mbps	N/A	√	√	√	via HPS	√
	Configuration via HPS	16 bits	100 MHz	1600 Mbps	N/A	√	√		via HPS	√
	Fast Passive Parallel (FPP)	32 bits	100 MHz	3200 Mbps	N/A	√	√		Parallel Flash Loader IP core	√
		16 bits	100 MHz	1600 Mbps		√
		8 bits	100 MHz	800 Mbps		√
	Active Serial (AS)	4 bits	100 MHz	400 Mbps	√	√	√⁽³⁾		√	√
	Active Serial (AS)	1 bit	100 MHz	100 Mbps	√	√	√⁽³⁾		√	√
	Passive Serial (PS)	1 bit	100 MHz	100 Mbps	N/A	√	√⁽³⁾		Parallel Flash Loader IP core	√
	JTAG	1 bit	33 MHz	33 Mbps	N/A		√⁽³⁾		N/A	√
Cyclone® 10 GX	Fast Passive Parallel (FPP)	32 bits	100 MHz	3200 Mbps	N/A	√	√	√	Parallel Flash Loader IP core	√
		16 bits	100 MHz	1600 Mbps		√
		8 bits	100 MHz	800 Mbps		√
	Active Serial (AS)	4 bit	100 MHz	400 Mbps	√	√	√⁽³⁾		√	√
	Active Serial (AS)	1 bits	100 MHz	100 Mbps	√	√	√⁽³⁾		√	√
	Passive Serial (PS)	1 bit	100 MHz	100 Mbps	N/A	√	√⁽³⁾		Parallel Flash Loader IP core	√
	JTAG	1 bit	33 MHz	33 Mbps	N/A	N/A	√⁽³⁾		N/A	√
Cyclone® 10 LP	Fast Passive Parallel (FPP)	8 bits	66⁽⁴⁾/100⁽⁶⁾ MHz	528⁽⁴⁾/800⁽⁶⁾ Mbps	N/A	N/A	N/A	√	Parallel Flash Loader IP core	√
	Passive Serial (PS)	1 bit	66⁽⁴⁾/133⁽⁵⁾ MHz	66⁽⁴⁾/133⁽⁵⁾ Mbps	N/A	N/A	N/A		Parallel Flash Loader IP core	√
	Active Serial (AS)	1 bit	40 MHz	40 Mbps	N/A	N/A	N/A		√	√
	JTAG	1 bit	25 MHz	25 Mbps	N/A	N/A	N/A		N/A	√
MAX® 10						√		√	√
Stratix® V						√		√	√
Arria® V						√		√	√
Cyclone® V						√		√	√
Stratix® IV						√		√	√
Cyclone® IV E						-		√	√
Cyclone® IV GX						-		√	√
Stratix® III						√		√	√
Cyclone® III LS						√		√	√
Cyclone® III						-		√	√
Arria® II GX						√		√	√
Cyclone® II						-		√	-

Notes:

The maximum clock rate when using OSC_CLK_1 as configuration clock source. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Partial Reconfiguration User Guide.
Partial configuration can be performed only when it is configured as internal host.
Supply voltage for internal logic, VCCINT = 1.0 V.
Supply voltage for internal logic, VCCINT = 1.2 V.
Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.

2. Configuration Schemes and IP

Configuration User Guides

Agilex™ 7 Devices

Agilex™ 7 Configuration User Guide

Agilex™ 5 Devices

Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

Stratix 10® Devices

Stratix® 10 Configuration User Guide

Configuration via HPS

Configure the FPGA portion of the SoC device by utilizing Hard Processor System (HPS)

Agilex™ 7 Devices

Agilex™ 7 Hard Processor System Technical Reference Manual

Agilex™ 5 Devices

Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs

Agilex™ 3 Devices

Hard Processor System Technical Reference Manual: Agilex™ 3 SoCs

Stratix® 10 Devices

Arria® 10 Devices

Fast Passive Parallel

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

FPGA Parallel Flash Loader IP Core User Guide

Active Serial

Agilex™ 7 Devices

Agilex™ 7 Configuration User Guide

Agilex™ 5 Devices

Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 Configuration User Guide

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Passive Serial

Arria® 10 GX Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

FPGA Parallel Flash Loader IP Core User Guide

JTAG

Agilex™ 7 Devices

Agilex™ 5 Devices

Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Configuration via Protocol (CvP)

Agilex™ 7 Devices

Agilex™ 7 Device Configuration via Protocol (CvP) Implementation User Guide

Agilex™ 5 Devices

Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Arria® 10 Devices

Cyclone® 10 GX Devices

3. Advanced Configuration Features

Device Security

FPGAs can decrypt a configuration bitstream using the advanced encryption standard (AES) algorithm. When using the design security feature, a security key is stored in the FPGA. To successfully configure an FPGA that has the design security feature enabled, you must configure the FPGA with a configuration file that was encrypted using the same security key. Some FPGAs offer both volatile and non-volatile security key storage. The volatile security key storage requires battery back-up but enables the security key to be updated. The non-volatile security key can be stored in non-volatile memory inside the device and does not require battery back-up for storage.

Agilex™ Family and Stratix® 10 Devices

Security Overview for SDM-Based FPGA Devices

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Additional Resources:

AN 556: Using the Design Security Features in FPGAs

AN 512: Using the Design Security Feature - Stratix III

AN 341: Using the Design Security Feature - Stratix II

Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA resources. PR enables the implementation of more complex FPGA systems.

Quartus® Prime Pro Edition User Guide: Partial Reconfiguration - Agilex™ 7, Agilex™ 5, and Agilex™ 3 devices, Stratix® 10 devices, Arria® 10 devices, Cyclone® 10 GX devices

Quartus® Prime Standard Edition User Guide: Partial Reconfiguration - Stratix® V device family and Cyclone® V devices whose part number ends in "SC", for example, 5CGXFC9E6F35I8NSC.

Agilex™ Family Devices

Partial Reconfiguration Solutions IP User Guide

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 GX Devices

Partial Reconfiguration Solutions IP User Guide

Additional Resources:

Decompression Support

Some FPGAs support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to the FPGA. During configuration, the FPGA decompresses the bitstream in real time and configures its CRAM cells.

Remote System Update

Altera devices have dedicated remote system upgrade circuitry. Soft logic (either the Nios® V embedded processor or user logic) implemented in the device that can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry helps to avoid system downtime.

Agilex™ 7 Devices

Agilex™ 7 Configuration User Guide

Agilex™ 5 Devices

Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Remote Update FPGA IP Core User Guide

Single Event Upset (SEU) Mitigation

Agilex™ 7 Devices

Agilex™ 7 SEU Mitigation User Guide

Agilex™ 5 Devices

SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

SEU Mitigation User Guide: Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 SEU Mitigation User Guide

Arria® 10 Devices

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

Flash Access IP

Agilex™ 7 Devices

Agilex™ 5 and Agilex™ 3 Devices

Mailbox Client FPGA IPs User Guide

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 GX Devices

Cyclone® 10 LP Devices

Chip ID IP

Agilex™ 7 Devices

Agilex™ 5 and Agilex™ 3 Devices

Mailbox Client FPGA IPs User Guide

Stratix® 10 Devices

Chip ID FPGA IP Cores User Guide

Arria® 10 Devices

Chip ID FPGA IP Cores User Guide

Cyclone® 10 GX Devices

Chip ID FPGA IP Cores User Guide

4. Quartus® Prime Software Design Flow

Table 2 - Device Configuration Setting and Programming Files Generation Flow

Topic	Description
General Setting	General page of the Device and Pin Options dialog box in the Quartus Prime Software. Specify the device options. These options are independent on the configuration scheme.
Configuration Setting	Configuration page of the Device and Pin Options dialog box in the Quartus Prime Software. Specify the Device Configuration scheme, Configuration Device setting and Configuration Pin setting.
Programming Files Setting	Programming Files page of the Device and Pin Options dialog box in the Quartus Prime Software. Select the programming file format to generate. Selecting the programming file in this page is optional, user is recommended to use the Convert Programming File or Programming File Generator to convert/generate the type of programming file for the used of selected configuration scheme.
Others Optional Advanced Feature Setting	Error Detection CRC, CvP Settings and Partial Reconfiguration page of the Device and Pin Options dialog box in the Quartus Prime Software. Error Detection CRC page - Specify whether error detection is used and the rate at which it is checked. CvP Settings page - Specify the type of CvP settings. Partial Reconfiguration page - Specify Partial Reconfiguration settings.
Generate Configuration and Programming Files	Once design compilation is completed, the Convert Programming Files or Programming File Generator is the tool in Quartus Prime Software to convert/generate the type of programming file for selected configuration scheme or configuration feature.

Where Can I Find Information on Device Configuration Settings and Configuration & Programming Files Generation?

Agilex™ 7 Devices

Agilex™ 7 Configuration User Guide

Agilex™ 5 Devices

Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 Configuration User Guide

Arria® 10 Devices

Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

5. Board Design

Where Can I Find Information on Device Configuration Design Guidelines?

Agilex™ 7 Devices

AN 886: Agilex™ 7 Device Design Guidelines

Agilex™ 5 Devices

Agilex™ 3 Devices

Device Design Guidelines: Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 Device Design Guidelines

Arria® 10 Devices

Cyclone® 10 GX Devices

Cyclone® 10 GX Device Design Guidelines

Where Can I Find Information on the Connection Guidelines for Configuration Pin?

Agilex™ 7 Devices

Agilex™ 7 Device Family Pin Connection Guidelines

Agilex™ 5 Devices

Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

Stratix® 10 Device Family Pin Connection Guidelines

Arria® 10 Devices

Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Cyclone® 10 GX Devices

Cyclone® 10 GX Device Family Pin Connection Guidelines

Cyclone® 10 LP Devices

Cyclone® 10 LP Device Family Pin Connection Guidelines

Where Can I Find Information on Configuration Specifications?

The configuration specification in the device datasheet specifies the following specifications:

Timing specifications for configuration control pins
Timing/Performance specifications for each of the supported configuration scheme
Configuration bit stream sizes

Agilex™ 7 Devices

Agilex™ 7 Device Datasheet

Agilex™ 5 Devices

Agilex™ 5 FPGAs and SoCs Device DataSheet

Agilex™ 3 Devices

Agilex™ 3 FPGAs and SoCs Device DataSheet

Stratix® 10 Devices

Stratix® 10 Device Datasheet

Arria® 10 Devices

Cyclone® 10 GX Devices

Cyclone® 10 LP Devices

6. Debug

Configuration debugger tool helps you debug programming and configuration issues. This tool is supported in Quartus® Prime Pro Edition Programmer version 21.3 onwards.

AN 955: Programmer’s Configuration Debugger Tool

FPGA Configuration Troubleshooter

Agilex™ 7 and Stratix® 10 FPGA System Console Debugging Tool Using JTAG

AN 936: Executing SDM Commands via JTAG Interface

Stratix® 10 FPGA SDM Debug Toolkit helps you debug your configuration issues.

It is available in Quartus Prime Pro Edition software v18.1 and onwards.

Searching a tool to debug configuration failures / design security / error detection cyclic redundancy check (CRC) on Arria® 10 devices?

To get this configuration diagnostic tool, please contact your Altera sales representative.

You can use this troubleshooter, fault tree analysis or troubleshooting guides to identify possible configuration failure causes.

Knowledge Base Solution

Go to Knowledge Base, enter the keywords of the issue you face to find for the solution.

Supported Flash Memory Devices (Configuration Devices)

Table 3 - FPGA Configuration Devices

Configuration Device Family	Capacity	Package	Voltage	FPGA Product Family Compatibility
EPCQ-A†	4 Mb - 32 Mb	8-pin SOIC	3.3 V	Compatible with Stratix® V, Arria® V, Cyclone® V, Cyclone® 10 LP and earlier FPGA families.
EPCQ-A†	64 Mb - 128 Mb	16-pin SOIC	3.3 V	Compatible with Stratix® V, Arria® V, Cyclone® V, Cyclone® 10 LP and earlier FPGA families.
Notes: † EPCQ-A family is supported from Quartus® Prime Standard Edition Software v17.1 onwards. For product family support for legacy families not included in version 17.1 file a Service Request. See also Configuration Devices.

Table 4 - Supported Third Party Configuration Devices

FPGA	Vendor	Part Number		Byte addressing	Dummy Clock Settings		Permanent Quad-Enabled flash?	Support Category
		Prefix	Suffix		ASx1	ASx4
Agilex™ 7⁽²⁶⁾	Micron	MT25QU128	ABA8E12-0AAT	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Altera Tested and Supported
		MT25QU256	ABA8E12-0AAT
		MT25QU512	ABB8E12-0AAT
		MT25QU01G	BBB8E12-0AAT
		MT25QU02G	CBB8E12-0AAT
	Macronix⁽¹⁰⁾	MX25U12835F	XDI-10G	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Altera Tested and Supported
		MX25U25643G	XDI00					Known to Work⁽¹³⁾
		MX25U25645G	XDI00					Altera Tested and Supported
		MX25U51245G	XDI00
		MX66U1G45G	XDI00
		MX66U2G45G	XRI00
	ISSI	IS25WP256E	-RHLE	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		IS25WP512M	-RHLE
		IS25WP01G	-RHLE⁽²²⁾
	Gigadevice	GD25LB512ME	BFRY⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		GD25LT512ME	BIRY⁽²³⁾
		GD55LB01GE	BIRY⁽²³⁾
		GD55LT01GE	BFRY⁽²³⁾
		GD55LB02GE	BIR⁽²³⁾
	Winbond	W25Q512NW	FIA⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		W25Q02NW	TBIA					Known to Work⁽¹¹⁾
		W25Q01NW	TBIA					Known to Work⁽¹¹⁾
Agilex™ 5 and Agilex™ 3	Support generic QSPI flash controllers that are capable of supporting any Quad SPI flash devices that meet both the following criteria. Supports Serial Flash Discoverable Parameter (SFDP) standard Supports dedicated pin reset Altera recommends you use QSPI flash devices from Micron, Macronix and ISSI*. The quad SPI device that meets the above both criteria is supported by Quartus Programming File Generator Tools and Quartus Programmer version 24.1 Pro Edition or newer versions. For more information, refer to Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.
Stratix® 10	Micron	MT25QU128	ABA8ESF-0SIT	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QU256	ABA8E12-1SIT
		MT25QU512	ABB8ESF-0SIT
		MT25QU01G	BBB8ESF-0SIT					AlteraTested and Supported
		MT25QU02G	CBB8E12-0SIT					Known to Work⁽¹¹⁾
	Macronix⁽¹⁰⁾	MX25U12835F	MI-100	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U25643G	XDI00					Known to Work⁽¹³⁾
		MX25U25645G	XDI00
		MX25U51245G	XDI00
		MX66U51235F	XDI-10G					Known to Work⁽¹¹⁾
		MX66U1G45G	XDI00					Known to Work⁽¹¹⁾
		MX66U2G45G	XRI00					Altera Tested and Supported
	ISSI	IS25WP256E	-RHLE	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		IS25WP512M	-RHLE
		IS25WP01G	-RILE⁽²²⁾
	Gigadevice	GD25LB512ME	BFRY⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		GD25LT512ME	BIRY⁽²³⁾
		GD55LB01GE	BIRY⁽²³⁾
		GD55LT01GE	BFRY⁽²³⁾
		GD55LB02GE	BIR⁽²³⁾
	Winbond	W25Q512NW	FIA⁽²³⁾	3-byte⁽¹⁾	N/A	Note⁽¹⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		W25Q02NW	TBIA					Known to Work⁽¹¹⁾
		W25Q01NW	TBIA					Known to Work⁽¹¹⁾
Arria® 10 Cyclone® 10 GX	Micron	MT25QU256	ABA8E12-1SIT	4-byte⁽⁴⁾	10⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QU512	ABB8ESF-0SIT					Known to Work⁽¹³⁾
		MT25QU512	ABB8E12-0SIT					Known to Work⁽¹²⁾
		MT25QL512	ABA8ESF-0SIT
		MT25QL512	ABB8ESF-0SIT
		MT25QU01G	BBB8ESF-0SIT					Known to Work⁽¹³⁾
		MT25QU01G	BBB8E12-0SIT					Known to Work⁽¹²⁾
		MT25QU01G	BBA8E12-0SIT					Known to Work⁽¹²⁾
		MT25QU02G	CBB8E12-0SIT					Known to Work⁽¹³⁾
	Macronix	MX25U256	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U512	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25U512	45GMI00⁽¹⁸⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66L512	35FMI-10G⁽¹⁹⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66U1G	45GXDI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
		MX66L1G	45GMI-10G⁽²⁰⁾	3-byte⁽¹⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MX66U2G	45GXRI54⁽³⁾	4-byte⁽⁵⁾	10⁽⁵⁾	10⁽⁵⁾	Yes⁽⁶⁾	Known to Work⁽¹¹⁾
	Cypress/Infineon	S25FS512	SDSBHV210	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		S25FL512⁽²⁵⁾	AGMFI011
		S70FL01G⁽²⁵⁾	SAGMFI011
Stratix® V Arria® V Arria® V SoC Cyclone® V Cyclone® V SoC	Micron	MT25QL128	ABA8ESF-0SIT	3-byte⁽¹⁾	12⁽⁴⁾	12⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QU128	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QU256	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QL256	ABA8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL512	ABB8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL512	ABA8ESF-0SIT	3-byte⁽¹⁾	10⁽¹⁾	10⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
		MT25QL01G	BBB8ESF-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MT25QL02G	CBB8E12-0SIT	4-byte⁽⁴⁾	4⁽⁴⁾	10⁽⁴⁾	No⁽⁶⁾	Known to Work⁽¹¹⁾
	Macronix	MX25L128	33FMI-10G⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		MX25L256	45GMI-08G⁽¹⁶⁾					Known to Work⁽¹³⁾
		MX25L256	35FMI-10G⁽¹⁶⁾					Known to Work⁽¹²⁾
		MX25L512	45GMI-08G⁽¹⁵⁾					Known to Work⁽¹³⁾
		MX66L512	35FMI-10G⁽¹⁵⁾					Known to Work⁽¹²⁾
		MX25U512	45GMI00⁽¹⁶⁾
		MX25U512	45GXDI00⁽¹⁶⁾
		MX66L1G	45GMI-10G⁽¹⁶⁾
		MX66U2G	45GXR100⁽¹⁵⁾
	Cypress/Infineon	S25FL128⁽²⁵⁾	SAGMFI000	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	6⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹³⁾
		S25FL256⁽²⁵⁾	SAGMFI000
		S25FL512⁽²⁵⁾	SAGMFI010
		S25FL512⁽²⁵⁾	SAGMFIG11					Known to Work⁽¹²⁾
		S70FL01G⁽²⁵⁾	SAGMFI011⁽¹⁷⁾					Known to Work⁽¹²⁾
	Gigadevice	GD25Q127	CFIG⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	4⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
	Gigadevice	GD25Q256	DFIG⁽¹⁵⁾	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	4⁽¹⁾	No⁽⁶⁾	Known to Work⁽¹²⁾
Cyclone® 10 LP	Micron	MT25QL128	ABA8ESF-0SIT	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MT25QL256	ABA8ESF-0SIT
		MT25QL512	ABB8ESF-0SIT
		MT25QL01G	BBB8ESF-0SIT
		MT25QL02G	CBB8E12-0SIT
	Macronix	MX25L128	33FMI-10G	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		MX25L256	45GMI-08G
		MX25L512	45GMI-08G
	Cypress/Infineon	S25FL128⁽²⁵⁾	SAGMFI000	3-byte⁽¹⁾⁽²⁾	8⁽¹⁾	N/A	No⁽⁶⁾	Known to Work⁽¹¹⁾
		S25FL256⁽²⁵⁾	SAGMFI000
		S25FL512⁽²⁵⁾	SAGMFI0I0
Notes: Using the default setting of the configuration devices. When performing remote system upgrade, the start address of the images must be set within first 128 Mb. Arria® 10 and Cyclone® 10 GX devices support only Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54, MX66U2G45GXRI54. Quartus Programmer set the non-volatile configuration register during programming operation. User need to set the register manually if using a third-party programmer. The configuration devices is permanent to this value, user do not have the options to change this setting. Quartus Programmer issues command to enable quad mode These configuration devices are not supported by legacy ASMI Parallel I FPGA IP core and ASMI Parallel II FPGA IP core. For new design, please refer to Generic Serial Flash Interface FPGA IP core. AS x 1 - Active serial configuration support 1 bit data width AS x 4 - Active serial configuration scheme support 4 bit data width Agilex™ 7 and Stratix® 10 devices do not support Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54. Tested with FPGA configuration. Tested with HPS. Tested with FPGA configuration and HPS. FPGA boot ROM perform normal READ operation to load the firmware which is initial part of the bit stream, after firmware is loaded, it reads the Serial Flash Discovery Parameter(SFDP) table defined by flash vendor to determine the number of dummy clock cycles for performing Quad I/O FAST READ operation to load the rest of the bit stream. U-Boot updates needed. U-Boot used for flashing. U-Boot updates needed. Two chip selects. HPS Flash Programmer and BootROM use only CS0. U-Boot modifications needed Programmed with U-Boot Programmed with modified U-Boot S70FS01G is incompatible with Arria® 10 and Cyclone® 10 GX device. You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x9d 0x70 0x1b, Device density=1024Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Quartus Prime Pro Edition. You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x00 0x00 0x00, Device density=512Mb/1024Mb/2048Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Quartus Prime Pro Edition. You need to define New Flash Memory Configuration Device based on programming flow template: Need to add part to Programmer: Device ID=0x9d 0x70 0x1b, Device density=1024Mb, Total device die=1, Programming flow template=Issi. Refer to add a custom flash device in Generic Flash Programmer User Guide: Quartus Prime Pro Edition. The Quartus Prime software does not support the flash specification 'CS# toggle with no CLK and Data is considered as non-valid,' which affects certain configuration devices within the S25FL-S family and S70FL01GS. In Agilex™ 7 F & I-Series devices, when the SDM runs the boot ROM firmware, it takes about 800ns to reset the flash memory using the AS_nRST reset pin before reading from the flash memory. This may violate the reset timing specification from QSPI flash memory vendors Macronix, Winbond and ISSI. Due to this, the SDM may fail to read the flash memory and may get stalled at the boot ROM phase. To workaround this problem, toggle the nCONFIG to recover from this issue and reconfigure the device.
Table 3 shows the criteria of third party configuration devices supported by Quartus Convert Programming File Tools/Programming File Generator and Quartus Programmer version 21.3 Pro Edition and 20.1 Standard Edition onwards. Altera tested and supported: These devices receive regression testing with FPGA tools and their use is fully supported by Altera FPGA Technical Support. Known to work: These devices are supported by Quartus Convert Programming File Tools or Programming File Generator Tools and Quartus Programmer version 21.3 Pro Edition or 20.1 Standard Edition or newer versions. For devices not explicitly listed in the Configuration Device list in Programming File Generator Tools, you can define a custom device using the available menu options.

Design Examples and Reference Designs

Design Store

Agilex™ 7 Devices

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 GX Devices

Cyclone® 10 LP Devices

Table 5 - Training Courses and Videos

FPGA Technical Training Catalog

Video Title	Description
Introduction to Configuring FPGAs	Learn the configuration schemes, solutions, features and tools available for configuring FPGAs and programming configuration devices.
Configuration Schemes for FPGAs	Learn the difference between all the configuration schemes that can be used to configure FPGAs.
Configuration for Stratix® 10 Devices	Learn the unique configuration features available in the Stratix® 10 devices.
Remote System Upgrade in MAX® 10 Devices	Learn how to set up and perform a RSU in an MAX® 10 device.
Creating Second Stage Bootloader for FPGA SoCs	Learn the flow and tools available to quickly customize and generate the second stage boot software.
Mitigating Single Event Upsets in Arria® 10 and Cyclone® 10 GX Devices	Learn the features of the Arria® 10 and Cyclone® 10 GX device families that can be used in the designing your own SEU mitigation solution.
SEU Mitigation in FPGA Devices: Hierarchy Tagging	Learn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging.
SEU Mitigation in FPGA Devices: Fault Injection	Learn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate.
Using the Generic Serial Flash Interface	Learn how to use the Generic Serial Flash Interface FPGA IP Core to program any serial peripheral interface (SPI) type flash device.
Partial Reconfiguration for FPGA Devices: Introduction & Project Assignments	Partial Reconfiguration Training part 1 of 4. This part of the training introduces you to the PR feature and the general design flow for a PR design. You'll also learn about design partition and Logic Lock region assignments, required assignments for implementing a PR design, and recommendations for how to floorplan a design for PR.
Partial Reconfiguration for FPGA Devices: Design Guidelines & Host Requirements	Partial Reconfiguration Training part 2 of 4. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations.
Partial Reconfiguration for FPGA Devices: PR Host IP & Implementations	Partial Reconfiguration Training part 3 of 4. This part of the training discusses all of the PR IP included in the Quartus Prime software, including the PR Controller IP, Region Controller IP, and Freeze Bridge IP. You'll also see how to use these IP to implement either an internal or external host design.
Partial Reconfiguration for FPGA Devices: Output Files & Demonstration	Partial Reconfiguration Training part 4 of 4. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Arria® 10 GX development kit.

Table 6 - Additional Videos

FPGA Quick Videos

Video Title	Description
Implementing a Partial Reconfiguration Design within Qsys for FPGAs	Watch this video to learn how to implement Partial Reconfiguration Design within Qsys for FPGAs.
Arria® 10 Configuration via Protocol (CvP)	Watch this video to learn how to configure your Arria® 10 device using the PCIe protocol.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2	Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP Core	Watch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.

For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.

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Device Configuration Support Center

1. Device Specific Configuration Details

Table 1 - Configuration Schemes and Features Overview

2. Configuration Schemes and IP

Configuration User Guides

Configuration via HPS

Fast Passive Parallel

Active Serial

Passive Serial

JTAG

Configuration via Protocol (CvP)

3. Advanced Configuration Features

Device Security

Partial Reconfiguration

Decompression Support

Remote System Update

Single Event Upset (SEU) Mitigation

Flash Access IP

Chip ID IP

4. Quartus® Prime Software Design Flow

Table 2 - Device Configuration Setting and Programming Files Generation Flow

Where Can I Find Information on Device Configuration Settings and Configuration & Programming Files Generation?

5. Board Design

Where Can I Find Information on Device Configuration Design Guidelines?

Where Can I Find Information on the Connection Guidelines for Configuration Pin?

Where Can I Find Information on Configuration Specifications?

6. Debug

Supported Flash Memory Devices (Configuration Devices)

Table 3 - FPGA Configuration Devices

Table 4 - Supported Third Party Configuration Devices

Design Examples and Reference Designs

Table 5 - Training Courses and Videos

Table 6 - Additional Videos

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