The DisplayPort IP Support Center is organized into industry-standard stages, which provides you with various resources to plan, select, design, implement, and verify your DisplayPort IP cores for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the DisplayPort links. This page is organized into categories that align with a DisplayPort system design flow from start to finish.

Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

What features are supported in the DisplayPort IP?

Which FPGA Device Family Should I Use?

Link Rate Supported by Device Family

The table below shows the resource information for Arria® V and Cyclone® V devices using M10K; Arria® 10, Stratix® 10, and Stratix® V devices using M20K.

The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 1 pixel per clock

What is the DisplayPort FPGA IP Core FPGA Resource Utilization?

Performance and Resource Utilization

The resource utilization data indicates typical expected performance for the DisplayPort FPGA IP.

The below table lists the resources and expected performance for selected variations. The results were obtained using the Quartus® Prime Pro Edition software version 20.2 for the following devices:

• Agilex™ F-tile (AGIB027R31B1E2VR0)
• Stratix® 10 (1SG280HU1F50E2VGS1)
• Arria® 10 (10AX115S2F45I1SG)
• Cyclone® 10 GX (10CX220YF780E5G)

DisplayPort 1.4 FPGA IP Resource Utilization

The table below shows the resource information for Agilex™ 7, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices using M20K. The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 1 pixel per clock, 4 pixel per clock for Agilex™ 7

DisplayPort 2.0 FPGA IP Resource Utilization

The table below shows the resource information for Stratix® 10 devices using the M20K. The resource count for the DP2.0 includes the resource count for the DP1.4 as well. The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 4 pixel per clock

HDCP Resource Utilization

The table lists the HDCP resource data for DisplayPort FPGA IP with configurations of SST (single stream) and at maximum lane of 4 configuration for Arria® 10 and Stratix® 10 devices.

What is the DisplayPort related information and documentation available?

Agilex™ 7 (F-tile), Stratix® 10 (H-tile and L-tile), Arria® 10, Cyclone® 10 GX, Arria® V GX/GT/GS, Arria® V GZ, Cyclone® V, Stratix® V

• DisplayPort FPGA IP User Guide

How do I generate the DisplayPort IP core?

Steps to generate DisplayPort IP Core in the Quartus® Prime software can be found in the chapter for Specifying IP Parameters and Options.

• DisplayPort FPGA IP User Guide
• DisplayPort FPGA IP Design Example User Guide: Agilex™ 5 FPGAs

What is supported in the Quartus® generated DisplayPort design example?

The DisplayPort FPGA IP core design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module. The below table illustrates design example options available for Agilex™ 7, Stratix® 10, Arria® 10 and Cyclone® 10 GX devices.

How do I generate the Quartus® DisplayPort design example?

For Agilex™ 7, Agilex™ 5, Stratix®, Arria® 10, and Cyclone® 10 GX devices, use the DisplayPort FPGA parameter editor in the Quartus® Prime Pro Edition software to generate the design example.

1. Click Tools IP Catalog, and select target device family.
2. In the IP Catalog, locate and double-click DisplayPort FPGA IP. The New IP Variation window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named ip.
4. You may select a specific FPGA device in the Device field, or keep the default Quartus® Prime software device selection.
5. Click OK. The parameter editor appears.
6. Configure the desired parameters for both TX and RX.
7. On the Design Example tab, select the design example that fits your criteria.
8. Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
9. For Target Development Kit, select the available FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit.
10. Click Generate Example Design.

Similarly, the links below provides step-by-step instruction to generate

DisplayPort design example from the Quartus® Prime software:

• DisplayPort Agilex™ 7 F-Tile FPGA IP Design Example User Guide
• DisplayPort Agilex™ 5 FPGA IP Design Example User Guide
• DisplayPort Stratix® 10 FPGA IP Design Example User Guide
• DisplayPort Arria® 10 FPGA IP Design Example User Guide
• DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

How do I compile and test my design?

For Agilex™ 7 and 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design

Compiling and Testing the Design:

• Compiling and Testing for Agilex™ 7 F-Tile
• Compiling and Testing for Agilex™ 5
• Compiling and Testing for Stratix® 10
• Compiling and Testing for Arria® 10
• Compiling and Testing for Cyclone® 10 GX

How can I perform DisplayPort functional simulation?

For Agilex™ 7, Stratix®, Arria® 10, and Cyclone® 10 GX devices, below are the steps to generate DisplayPort functional simulation:

Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example.

Simulating Design:

• Simulating Design for Agilex™ 7 F-Tile
• Simulating Design for Agilex™ 5
• Simulating Design for Stratix® 10
• Simulating Design for Arria® 10
• Simulating Design for Cyclone® 10 GX

Simulation Testbench:

• Simulation Testbench for Agilex™ 7 F-Tile
• Simulation Testbench for Agilex™ 5
• Simulation Testbench for Stratix® 10
• Simulation Testbench for Arria® 10
• Simulation Testbench for Cyclone® 10 GX

Where do I find information on the Clock Recovery Core?

The Agilex™ 7, Stratix®, Arria® 10, and Cyclone® 10 GX DisplayPort design example uses Pixel Clock Recovery IP.

Clock Recovery Core information:

• DisplayPort IP Core User Guide

Where do I find information on the DisplayPort Link Training flow?

Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink.

DisplayPort Link Training Flow:

• DisplayPort IP Core User Guide

Where do I find information on the DisplayPort API reference and DPCD information?

The following resources will provide instructions for the DisplayPort application programming interface (API) reference and DPCD:

• Source-supported DPCD locations
• Sink-supported DPCD locations
• DisplayPort FPGA IP User Guide

Pin Connection Guidelines

Agilex™ 7 Devices

• Agilex™ 7 Device Family Pin Connection Guideline: F-Series and I-Series
• Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

Agilex™ 5 Devices

• Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

Agilex™ 3 Devices

• Pin Connection Guidelines: Agilex™ 3 FPGAs and SoCs

Stratix® 10 Devices

• Stratix® 10 GX, MX, TX and SX Device Family Pin Connection Guidelines

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines

Cyclone® 10 GX Devices

• Cyclone® 10 GX Device Family Pin Connection Guidelines

Schematic Review

Agilex™ 7 Devices

• Agilex™ 7 Schematic Review Worksheet: F-Series and I-Series
• Agilex™ 7 Device Schematic Review Worksheet: M-Series

Agilex™ 5 Devices

• Agilex™ 5 Device Schematic Review Worksheet: D-Series and E-Series

Agilex™ 3 Devices

• Agilex™ 3 Device Schematic Review Worksheet

Stratix® 10 Devices

• Stratix® 10 GX, MX, and SX Schematic Review Worksheet
• Stratix® 10 GX FPGA Development Kit User Guides and Schematics
• Stratix® 10 SX SoC Development Kit User Guides and Schematics

Arria® 10 Devices

• Arria® 10 GX, GT, and SX Schematic Review Worksheet
• Arria® 10 GX FPGA Development Kit User Guides and Schematics
• Arria® 10 SoC Development Kit User Guides and Schematics

Cyclone® GX 10 Devices

• Cyclone® 10 GX Schematic Review Worksheet
• Cyclone® 10 GX FPGA Development Kit User Guides and Schematics

Board Design Guidelines

• Agilex™ 7 Devices Design Guidelines High-Speed Serial Interface Signal Integrity User Guide
• Agilex™ 5 PCB Design Guidelines (HSSI, EMIF, MIPI, True Differential, PDN) User Guide
• PCB Layout, Routing, and Power Distribution Network Design Guidelines: Agilex™ 3 FPGAs and SoCs
• AN 766: Stratix® 10 High-Speed Signal Interface Layout Design Guidelines User Guide
• AN 958: Board Design Guidelines Solutions
• Board Layout Test
• AN 114: Board Design Guidelines for Programmable Device Packages
• AN 613: PCB Stackup Design Considerations for FPGAs
• AN745: Design Guideline for FPGA DisplayPort Interface
• FMC DisplayPort Daughter Card Revision 8 Schematics
• FMC DisplayPort Daughter Card Revision 11 Schematics
• HSMC DisplayPort 1.2 Daughter Card Schematics

Disclaimer: The Arria® 10 and Stratix® 10 Development Kit on-board DisplayPort TX board design implementation is NOT recommended as it does not allow PMA + PCS bonding. Users are advised to refer to the Bitec design implementation.

Power Management

• AN 910: Agilex™ 7 Power Distribution Network Design Guidelines
• Agilex™ 7 Power Management User Guide
• Agilex™ 5 Power Management User Guide
• Agilex™ 3 Power Management User Guide
• Stratix® 10 Power Management User Guide
• Stratix® 10 Early Power Estimator User Guide
• AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix 10, Arria® 10, and Cyclone® 10 GX Devices
• Arria® 10 Early Power Estimator User Guide
• AN 711: Arria® 10 Power Reduction Features
• Cyclone® 10 Early Power Estimator User Guide
• Early Power Estimator (EPE) and Power Analyzer
• AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
• AN 721: Creating an FPGA Power Tree
• Quartus® Prime Pro Edition User Guide Power Analysis and Optimization
• FPGA Power and Thermal Calculator User Guide

Thermal Power Management

Agilex™ Devices

• AN 944: Agilex™ 7 Thermal Modeling with the FPGA Power and Thermal Calculator (PCT)
• Agilex™ 5 Thermal Design User Guide with the Power and Thermal Calculator (PTC)
• Agilex™ 3 Thermal Design User Guide

Stratix® 10 Devices

• AN 787: Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
• AN 943: Stratix® 10 Thermal Modeling with the FPGA Power and Thermal Calculator (PCT)

Power Sequencing

Agilex™ 7, Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices

• AN 692: Power Sequencing Considerations for Agilex™ 7, Stratix® 10 Arria® 10, and Cyclone® 10 GX Devices

My design require Bitec FMC daughter card. How do I select them?

The following table provides a quick guideline in selecting Bitec FMC daughtercard revision.

Any requirement to use single or dual lanes transceiver channel with Bitec FMC daughter card for 10-series devices?

Yes. For DisplayPort design that uses/referred to in an early version of Bitec FMC daughtercard (revision 8 and earlier), the pin assignment in the following link has to be followed at TX and RX due to the lane reversal and polarity inversion at the channel.

How do I create a DisplayPort TX-only or RX-only design?

A general guideline to create a DisplayPort TX-only or RX-only design can be found in the DisplayPort Arria® 10 FPGA IP Design Example User Guide. Alternatively, a more detailed explanation specific to the DisplayPort TX-only design can be referred to in the AN 883: Arria® 10 DisplayPort TX-only Design User Guide.

Arria® 10 Devices

• AN 793: Arria® 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design
• Arria® 10 DisplayPort TX-only Design User Guide
• Arria® 10 FPGA – DisplayPort Using Onboard Connector (TX Only) Design Example
• DisplayPort UHD Scaler and Mixer Design Example User Guide
• AN 900: Arria® 10 DisplayPort 8K RX-only Design.
• AN 889: 8K DisplayPort Video Format Conversion Design Example

How do I debug my DisplayPort design?

Monitor link training completion status, link rate, and channel count on the development kit on-board user LED.

• DisplayPort Stratix® 10 FPGA IP Design Example User Guide

Monitor video Main Stream Attributes (MSA) information and auxiliary channel traffic of link training via Nios II terminal.

• DisplayPort FPGA IP User Guide
• AN 900: Arria® 10 DisplayPort 8K RX-only Design

Calculate the required video resolution bandwidth and its recovered clock.

• DisplayPort Bandwidth & PCR Calculator

Translate DisplayPort Link Training AUX Transaction

• DisplayPort Link Training AUX Translation Tool