Agilex™ 5 FPGA Interface Protocol Design Journey

Overview

infoGTS Ethernet FPGA Hard IP Overview

picture_as_pdfGTS Ethernet FPGA Hard IP Release Notes

picture_as_pdfGTS Auto-Negotiation and Link Training for Ethernet FPGA IP Release Notes

picture_as_pdfGTS Dynamic Reconfiguration Controller FPGA Release Notes

Design

picture_as_pdfGTS Ethernet FPGA Hard IP User Guide: For Agilex® 5 Devices

picture_as_pdfGTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

articleGTS Ethernet FPGA Hard IP Register Map

articleGTS Auto-Negotiation and Link Training IP Register Map

Debug

picture_as_pdfEthernet Toolkit User Guide

Overview

infoGTS Ethernet FPGA Hard IP Overview

picture_as_pdfGTS Ethernet FPGA Hard IP Release Notes

picture_as_pdfGTS Auto-Negotiation and Link Training for Ethernet FPGA IP Release Notes

Design

picture_as_pdfGTS Ethernet FPGA Hard IP User Guide

articleGTS Ethernet FPGA Hard IP Register Map

articleGTS Auto-Negotiation and Link Training IP Register Map

Debug

picture_as_pdfEthernet Toolkit User Guide

infoLow Latency Ethernet 10G MAC FPGA IP Overview

Overview

infoGTS Ethernet FPGA Hard IP Overview

picture_as_pdfGTS Ethernet FPGA Hard IP Release Notes

picture_as_pdfGTS Auto-Negotiation and Link Training for Ethernet FPGA IP Release Notes

picture_as_pdfLow Latency Ethernet 10G MAC FPGA IP Release Notes

Design

picture_as_pdfGTS Ethernet FPGA Hard IP User Guide

picture_as_pdfLow Latency Ethernet 10G MAC FPGA IP User Guide

picture_as_pdfLow Latency Ethernet 10G MAC FPGA IP Design Example User Guide

articleGTS Ethernet FPGA Hard IP Register Map

articleGTS Auto-Negotiation and Link Training IP Register Map

Debug

picture_as_pdfEthernet Toolkit User Guide

Overview

infoTriple-Speed Ethernet IP Overview

picture_as_pdfTriple-Speed Ethernet FPGA IP Release Notes

Design

picture_as_pdfTriple-Speed Ethernet FPGA IP User Guide

picture_as_pdfTriple-Speed Ethernet FPGA IP Design Example User Guide

picture_as_pdfGMII to RGMII Converter Core (Embedded Peripherals User Guide)

Debug

info1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP Overview

Overview

picture_as_pdf1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP Release Notes

picture_as_pdfGTS Dynamic Reconfiguration Controller FPGA Release Notes

Design

picture_as_pdf1G/2.5G/5G/10G Multirate Ethernet PHY FPGA IP User Guide

picture_as_pdfGTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 5 FPGAs and SoCs

Debug

Design

picture_as_pdfEthernet Design Example Components Release Notes

picture_as_pdfEthernet Design Example Components User Guide

Debug

Please select the desired Design With IO sub-step from the flowchart to the left to view the applicable assets:

Design with GPIO and LVDS IO
Design with PHY Lite IP

Please select the desired Design With Transceiver sub-step from the flowchart to the left to view the applicable assets:

Design with GTS Transceiver

Overview

picture_as_pdfGPIO FPGA IP Release Notes

picture_as_pdfLVDS SERDES FPGA IP Release Notes

picture_as_pdfLVDS Tunneling Protocol and Interface IP Release Notes

Design

picture_as_pdfGeneral-Purpose I/O User Guide

picture_as_pdfLVDS SERDES User Guide

picture_as_pdfLVDS Tunneling Protocol and Interface IP User Guide

Overview

picture_as_pdfPHY Lite for Parallel Interfaces FPGA IP Core Release Notes

Design

picture_as_pdfPHY Lite for Parallel Interfaces FPGA IP User Guide

Debug

Overview

picture_as_pdfSelecting from Transceiver Offerings

picture_as_pdfDevice Design Guidelines

picture_as_pdfGTS PMA/FEC Direct PHY IP Release Notes

infoGTS Transceiver Basics Training

infoTransceiver PHY IP - Support Center

infoTransceiver Toolkit Training

info17G Transceiver Demo Video

Design

picture_as_pdfGTS Transceiver PHY User Guide

picture_as_pdfGTS Transceiver Dual Simplex Interfaces User Guide

articleGTS Transceiver Clocking and Datapath Tool

articleGTS PMA/FEC Direct PHY IP Register Map

picture_as_pdfGTS Dynamic Reconfiguration Controller IP User Guide

Debug

picture_as_pdfGTS Transceiver Toolkit

lockTransceiver IBIS AMI Model (Sign-in and NDA Required)

articleGTS Transceiver TX Equalizer Tool

Plan

listIBIS Models for Altera® FPGA Devices

articleGTS Transceiver Reference Clock IBIS Models (zip)

Please select the desired Design with PCI Express (PCIe) IP sub-step from the flowchart to the left to view the applicable assets:

Discover PCIe IP Solutions
Add PCIe Gen 4 Interface

Please select the desired Design with DMA Controller sub-step from the flowchart to the left to view the applicable assets:

Add DMA Controller

Please select the desired Design With PHY Lite IP sub-step from the flowchart to the left to view the applicable assets:

Add PHY Lite Interface

Overview

infoFPGA IP for PCI Express

infoPCI Express IP - Support Center

listFPGA PCNs, PDNs, and ADVs

Overview

infoGTS AXI Streaming IP for PCI Express* Overview

picture_as_pdfGTS AXI Streaming IP for PCI Express* Release Notes

Design

picture_as_pdfGTS AXI Streaming IP for PCI Express* User Guide

picture_as_pdfGTS AXI Streaming IP for PCI Express* Design Example User Guide

picture_as_pdfGTS AXI Streaming IP for PCI Express* Register Map

picture_as_pdfMSI to GIC Generator Core Overview

Training

infoUsing GTS AXI Streaming IP for PCI Express*

Debug

Overview

infoPCIe* Multi Channel DMA IP Overview

picture_as_pdfGTS AXI Multichannel DMA IP for PCI Express* Release Notes

Design

picture_as_pdfGTS AXI Multichannel DMA IP for PCI Express User Guide

Debug

Overview

picture_as_pdfPHY Lite for Parallel Interfaces FPGA IP Core Release Notes

Design

picture_as_pdfPHY Lite for Parallel Interfaces FPGA IP User Guide

Debug

Please select the desired Design with Serial Lite Interface sub-step from the flowchart to the left to view the applicable assets:

Add GTS Serial Lite IV Interface

Please select the desired Design with Interlaken Interface sub-step from the flowchart to the left to view the applicable assets:

Add GTS Interlaken Interface

Overview

infoGTS Serial Lite IV FPGA IP Core Overview

picture_as_pdfGTS Serial Lite IV FPGA IP Release Notes

Design

picture_as_pdfGTS Serial Lite IV FPGA IP User Guide

picture_as_pdfGTS Serial Lite IV FPGA IP Design Example User Guide

Debug

Overview

infoGTS Interlaken FPGA IP Overview

picture_as_pdfGTS Interlaken FPGA IP Release Notes

Design

picture_as_pdfGTS Interlaken FPGA IP User Guide

picture_as_pdfGTS Interlaken FPGA IP Design Example User Guide

articleGTS Interlaken FPGA IP Register Map

Debug

Please select the desired Add DDR Memory Interfaces sub-step from the flowchart to the left to view the applicable assets:

Add DDR5 Memory Interface
Add DDR4 Memory Interface
Add LPDDR5 Memory Interface
Add LPDDR4 Memory Interface

Please select the desired Add Flash Memory Interfaces sub-step from the flowchart to the left to view the applicable assets:

Add QSPI Flash Interface
Add NAND Flash Interface
Add SD/MMC Flash Interface

Please select the desired Add On-Chip Memory sub-step from the flowchart to the left to view the applicable assets:

Add On-Chip Memory

Please select the desired Add DMA Controller sub-step from the flowchart to the left to view the applicable assets:

Add Modular Scatter-Gather DMA Core

Overview

infoDDR5 and DDR4 EMIF FPGA IP Overview

picture_as_pdfEMIF FPGA IP Core Release Notes

picture_as_pdfTest Engine FPGA IP Release Notes

picture_as_pdfPerformance Monitor FPGA IP Release Notes

Training

infoDDR5 Memory and Memory Interface IP Ask an Expert

infoFast and Easy I/O System Design with Interface Planner

EMIF Device Selection

infoExternal Memory Interface (EMIF) Mailbox Script

Design

picture_as_pdfEMIF IP User Guide

picture_as_pdfEMIF IP Design Example User Guide

picture_as_pdfTest Engine FPGA IP User Guide

picture_as_pdfPerformance Monitor FPGA IP User Guide

picture_as_pdfExternal Memory Interface for Hard Processor Subsystem (HPS)

Support Tools

picture_as_pdfExternal Memory Interface (EMIF) Debug Toolkit

Debug

Hard Processor System (HPS)

picture_as_pdfHard Processor System (HPS) Resources

picture_as_pdfDevice Design Guidelines

Overview

infoDDR5 and DDR4 EMIF FPGA IP Overview

picture_as_pdfEMIF FPGA IP Core Release Notes

picture_as_pdfTest Engine FPGA IP Release Notes

picture_as_pdfPerformance Monitor FPGA IP Release Notes

Training

infoFast and Easy I/O System Design with Interface Planner

EMIF Device Selection

infoExternal Memory Interface (EMIF) Mailbox Script

Design

picture_as_pdfEMIF IP User Guide

picture_as_pdfEMIF IP Design Example User Guide

picture_as_pdfTest Engine FPGA IP User Guide

picture_as_pdfPerformance Monitor FPGA IP User Guide

picture_as_pdfExternal Memory Interface for Hard Processor Subsystem (HPS)

Support Tools

picture_as_pdfExternal Memory Interface (EMIF) Debug Toolkit

Debug

Hard Processor System (HPS)

picture_as_pdfHard Processor System (HPS) Resources

picture_as_pdfDevice Design Guidelines

Overview

picture_as_pdfEMIF FPGA IP Core Release Notes

picture_as_pdfTest Engine FPGA IP Release Notes

picture_as_pdfPerformance Monitor FPGA IP Release Notes

Training

infoFast and Easy I/O System Design with Interface Planner

EMIF Device Selection

infoExternal Memory Interface (EMIF) Mailbox Script

Design

picture_as_pdfEMIF IP User Guide

picture_as_pdfEMIF IP Design Example User Guide

picture_as_pdfTest Engine FPGA IP User Guide

picture_as_pdfPerformance Monitor FPGA IP User Guide

picture_as_pdfExternal Memory Interface for Hard Processor Subsystem (HPS)

Support Tools

picture_as_pdfExternal Memory Interface (EMIF) Debug Toolkit

Debug

Hard Processor System (HPS)

picture_as_pdfHard Processor System (HPS) Resources

picture_as_pdfDevice Design Guidelines

Overview

picture_as_pdfEMIF FPGA IP Core Release Notes

picture_as_pdfTest Engine FPGA IP Release Notes

picture_as_pdfPerformance Monitor FPGA IP Release Notes

Training

infoFast and Easy I/O System Design with Interface Planner

EMIF Device Selection

infoExternal Memory Interface (EMIF) Mailbox Script

Design

picture_as_pdfEMIF IP User Guide

picture_as_pdfEMIF IP Design Example User Guide

picture_as_pdfTest Engine FPGA IP User Guide

picture_as_pdfPerformance Monitor FPGA IP User Guide

picture_as_pdfExternal Memory Interface for Hard Processor Subsystem (HPS)

Support Tools

picture_as_pdfExternal Memory Interface (EMIF) Debug Toolkit

Debug

Hard Processor System (HPS)

picture_as_pdfHard Processor System (HPS) Resources

picture_as_pdfDevice Design Guidelines

Overview

infoDevice Configuration Support Center

Design

picture_as_pdfMailbox Client IPs User Guide

picture_as_pdfGeneric Serial Flash Interface IP User Guide

picture_as_pdfHPS Use of SDM QSPI Controller

picture_as_pdfAN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices

Get Device Driver

picture_as_pdfHAL Driver - Generic Serial Flash Interface IP

picture_as_pdfHAL Driver - Mailbox Client IP

Design

picture_as_pdfNAND Flash Controller

Design

picture_as_pdfSD/eMMC Host Controller

Design

picture_as_pdfOn-Chip Memory II (RAM or ROM) IP

Design

picture_as_pdfModular Scatter-Gather DMA Core

Get Device Driver

picture_as_pdfHAL Driver - Modular Scatter-Gather DMA Core

Please select the desired Before You Begin sub-step from the flowchart to the left to view the applicable assets:

Discover Embedded Peripheral IP Portfolio

Please select the desired Design with General Purpose IO sub-step from the flowchart to the left to view the applicable assets:

Add General Purpose IO Soft IP
Add HPS GPIO Interface

Please select the desired Design with UART Interface sub-step from the flowchart to the left to view the applicable assets:

Add UART Soft IP Interface
Add JTAG UART Interface
Add HPS UART Controller

Please select the desired Design with JTAG Interface sub-step from the flowchart to the left to view the applicable assets:

Add JTAG Interface

Please select the desired Design with I2C Interface sub-step from the flowchart to the left to view the applicable assets:

Add I2C Soft IP Interface
Add HPS I2C Controller

Please select the desired Design with I3C Interface sub-step from the flowchart to the left to view the applicable assets:

Add HPS I3C Controller

Please select the desired Design with SPI Interface sub-step from the flowchart to the left to view the applicable assets:

Add SPI Interface
Add eSPI Interface
Add HPS SPI Controller

Please select the desired Design with USB Interface sub-step from the flowchart to the left to view the applicable assets:

Add HPS USB 2.0 OTG Controller
Add HPS USB 3.1 Gen1 Controller

Please select the desired Design with HPS Interface sub-step from the flowchart to the left to view the applicable assets:

Add Cache Coherency Translator

Overview

picture_as_pdfEmbedded Peripherals IP User Guide

picture_as_pdfTool Support

picture_as_pdfDevice Support

Overview

picture_as_pdfPIO Core Overview

picture_as_pdfGPIO FPGA IP Release Notes

picture_as_pdfGeneral-Purpose I/O User Guide

Overview

picture_as_pdfGeneral-Purpose I/O Interface Overview

Overview

picture_as_pdf16550 Compatible UART Core Overview

picture_as_pdfLightweight UART Core Overview

Drivers

picture_as_pdfHAL Driver - 16550 Compatible UART Core Overview

picture_as_pdfHAL Driver - Lightweight UART Core Overview

Overview

picture_as_pdfJTAG UART Core Overview

Drivers

picture_as_pdfHAL Driver - JTAG UART Core Overview

Overview

picture_as_pdfUART Controller Overview

picture_as_pdfUART Interface Design Guidelines Overview

Overview

picture_as_pdfJTAG to Avalon® Host Bridge Cores Overview

Overview

picture_as_pdfAvalon® I2C (Host) Core Overview

picture_as_pdfI2C Agent to Avalon® - MM Host Bridge Core

Drivers

picture_as_pdfHAL Driver - Avalon® I2C (Host) Core

infoLinux Driver - Avalon® I2C (Host) Core

Overview

picture_as_pdfI2C Controller Overview

picture_as_pdfI2C Interface Design Guidelines

Overview

picture_as_pdfI3C Controller Overview

picture_as_pdfI3C Interface Design Guidelines

Overview

picture_as_pdfSPI Core

picture_as_pdfAvalon®-ST Serial Peripheral Interface Core Overview

picture_as_pdfSPI Agent to Avalon® Host Bridge Cores

Drivers

picture_as_pdfHAL Driver - SPI Core Overview

infoLinux Driver - SPI Core

Overview

picture_as_pdfeSPI Agent Core Overview

Overview

picture_as_pdfSPI Controller Overview

Overview

picture_as_pdfUSB 2.0 OTG Controller Overview

picture_as_pdfInterfacing a USB PHY to the HPS USB 2.0 OTG Controller

Overview

picture_as_pdfUSB 3.1 Gen1 Controller Overview

picture_as_pdfUSB 3.1 Gen1 Controller Design Guidelines

Overview

picture_as_pdfAltera ACE5-Lite Cache Coherency Translator FPGA IP

Please select the desired Design with Video Interfaces sub-step from the flowchart to the left to view the applicable assets:

Add DisplayPort Interface
Add SDI Interface
Add HDMI Interface
Add MIPI Interface

Please select the desired Design with Video and Vision Processing Suite sub-step from the flowchart to the left to view the applicable assets:

Add Video and Vision Processing Suite

Overview

infoDisplayPort IP Support Center

Design

picture_as_pdfDisplayPort FPGA IP User Guide

picture_as_pdfGTS DisplayPort FPGA IP Design Example User Guide

Debug

infoSerial Digital Interface II IP Support Center

Overview

picture_as_pdfSerial Digital Interface (SDI) II FPGA IP Release Notes

Design

picture_as_pdfGTS SDI II FPGA IP User Guide

picture_as_pdfGTS SDI II FPGA IP Design Example User Guide

picture_as_pdfSDI Audio FPGA IP User Guide

Debug

Design

picture_as_pdfGTS HDMI FPGA IP User Guide

picture_as_pdfGTS HDMI FPGA IP Design Example User Guide

Debug

infoCommon Public Radio Interface (CPRI) FPGA IP Overview

Design

picture_as_pdfMIPI CSI-2 FPGA IP User Guide

picture_as_pdfMIPI CSI-2 FPGA IP Design Example User Guide

picture_as_pdfMIPI DSI-2 IP User Guide

picture_as_pdfMIPI D-PHY IP User Guide

Design

picture_as_pdfVideo and Vision Processing Suite FPGA IP User Guide

picture_as_pdfAltera® FPGA Streaming Video Protocol Specification

Please select the desired Design with Wireless Radio Interfaces sub-step from the flowchart to the left to view the applicable assets:

Add CPRI
Add eCPRI
Add O-RAN Interface

Please select the desired Design with ADC/DAC Data Converter Interfaces sub-step from the flowchart to the left to view the applicable assets:

Add JESD204B Interface
Add JESD204C Interface

Please select the desired Design with Forward Error Correction IP sub-step from the flowchart to the left to view the applicable assets:

Add 5G LDPC Interface
Add 5G Polar Interface
Add Turbo Interface

Overview

picture_as_pdfGTS CPRI PHY FPGA IP Release Notes

Design

picture_as_pdfGTS CPRI PHY FPGA IP User Guide

picture_as_pdfGTS CPRI PHY FPGA IP Design Example User Guide

articleGTS CPRI PHY FPGA IP Register Map

Debug

infoenhanced Common Public Radio Interface (eCPRI) FPGA IP Overview

Overview

picture_as_pdfeCPRI FPGA IP Release Notes

picture_as_pdfeCPRI Common Public Radio Interface Specification

Design

picture_as_pdfeCPRI FPGA IP User Guide

picture_as_pdfeCPRI FPGA IP Design Example User Guide

Debug

infoKnowledge Base Solution for Altera® FPGA IPs

Overview

infoExtensible Radio Access Network (O-RAN) FPGA IP Overview

Design

picture_as_pdfO-RAN FPGA IP User Guide

picture_as_pdfO-RAN FPGA IP Design Example User Guide

Debug

Overview

infoJESD204B FPGA IP Overview

picture_as_pdfGTS JESD204B IP Release Notes

Design

picture_as_pdfGTS JESD204B IP User Guide

picture_as_pdfGTS JESD204B IP Design Example User Guide

Debug

Overview

infoJESD204C FPGA IP Overview

picture_as_pdfGTS JESD204C FPGA IP Release Notes: E-Series Devices

infoJESD204B/JESD204C IP - Support Center

Design

picture_as_pdfGTS JESD204C FPGA IP User Guide: E-Series Devices

picture_as_pdfGTS JESD204C FPGA IP Design Example User Guide: E-Series Devices

Debug