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GTS PCIe Hard IP

Altera

Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x4 (E-Series) and PCIe 4.0 x8 (D-Series) configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.

Agilex™ 3 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 3.0 x4 configurations for Root Port and Endpoint modes.

Key Features

  • Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers.
  • Broad PCIe Version Support – Agilex 5: PCIe 4.0/3.0 (x8/x4/x2/x1) and Agilex 3: PCIe 3.0 (x4/x2/x1), with seamless down-training to PCIe 2.0/1.0.
  • Flexible Port & Mode Options – Root Port, Endpoint, and Transaction Layer (TL) Bypass modes for optional 3rd-party switch IP integration.
  • Versatile Application Interfaces – AXI4-Stream for data: AXI4-Stream Source/Sink, and AXI-Lite for control and status.
  • High Performance Data Handling – Up to 512B Maximum Payload Size (MPS), 4KB Maximum Read Request Size (MRRS), and support for Atomic operations (Fetch/Add/Swap/CAS).
  • Scalable Tag & Transaction Support – Up to 512 outstanding tags on x8 controller (Agilex 5 FPGA) and up to 256 outstanding tags on x4 controller (Agilex 5 and Agilex 3 FPGAs).
  • Advanced Virtualization – SR-IOV (4 PFs, 256 VFs), Function Level Reset (FLR), and VirtIO for software-based virtualization.
  • Comprehensive Clocking and Efficiency Controls – Supports multiple clocking modes (Spread Spectrum: SRIS, SRNS supported), Precision Time Management (PTM), and power states (D0/D3).
  • Enhanced Reliability & Debug – Advanced Error Reporting, Design Tool Kit (DTK), and SpyGlass CDC analysis tool.
  • Comprehensive Software Support – Ready-to-use Linux device drivers for faster deployment.
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Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Compliance Link Compliance Link
Development Language Encrypted Verilog

Encrypted Verilog Source Code

Design Example(s)

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, Design Example User Guide, IP Release Notes

Ordering Information

Market Segment and Sub-Segments