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Multichannel DMA IP for PCI Express

Altera

The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility for HPC, data center, test, and medical applications. With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.

Key Features

  • Flexible Application Interfaces – Supports AXI-Stream, Avalon® Memory-Mapped, and Avalon® Streaming interfaces for broad system integration.
  • Optimized for Agilex FPGA Families – Delivers scalable DMA capabilities across Agilex 7 and Agilex 5 devices.
  • Root Port or Endpoint Configurability – Operates in either PCIe Root Port or Endpoint mode for versatile deployment.
  • High-Performance PCIe Connectivity – Supports up to PCIe 5.0 ×16 on Agilex 7 and up to PCIe 4.0 ×8 on Agilex 5 for maximum throughput.
  • Multiple Data Bus Options – 256-, 512-, and 1024-bit bus widths for Agilex 7 and 128-, 256-bit bus widths for Agilex 5 for optimal bandwidth and design flexibility.
  • Configurable Multichannel Architecture – Scales up to 2048 channels (Agilex 7) and up to 8 channels on Agilex 5, with Agilex 5 expansion to 256 channel support in future Quartus release.
  • Virtualization and SR-IOV Support – Enables up to 8 PFs / 2048 VFs (Agilex 7) and 1 PF / 8 VFs (Agilex 5), with additional PFs/VFs support in future Quartus release up to 4 PFs / 256 VFs on Agilex 5.
  • Advanced Transaction Management – 10-bit tag support, support for completion reordering and timeout handling, and head-of-line blocking prevention for reliable high-throughput performance.
  • Integrated MSI-X Interrupts – Simplifies DMA operation signaling and improves host-side efficiency.
  • Comprehensive Software Support – Ready-to-use Linux device drivers (Network Device, DPDK, and driver support for SR-IOV) for faster deployment.
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Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog Source Code

Design Example(s)

Simulation Models

IP Evaluation Mode

Documentation: IP User Guides, Design Example User Guides, IP Release Notes

Ordering Information

Market Segment and Sub-Segments