JESD204B and JESD204C IP Core Support Center

The JESD204B and JESD204C FPGA IP core support center provides information on how to select, design, implement and debug JESD204B and JESD204C links. This page is organized into categories that align with a JESD204B and JESD204C system design flow from start to finish.

1. Device and IP Selection 2. Design Flow and IP Integration 3. Board Design and Power Management 4. Interoperability and Standards Testing 5. IP and Design Examples User Guides 6. Training Courses and Videos 7. Debug

The JESD204B and JESD204C IP Core Support Center provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.

Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

Getting Started

1. Device and IP Selection

Which FPGA Family Should I Use?

Table 1 - JESD204B FPGA IP Core Performance

Device Family	PMA Speed Grade	FPGA Fabric Speed Grade	Data Rate		Link Clock fMAX (MHz)
			Enable Hard PCS (Gbps)	Enable Soft PCS (Gbps) 1
Agilex™ 7 (F-Tile)	1	-1	Not supported	2.0 to 20.0	data_rate/40
	1	-2	Not supported	2.0 to 19.2	data_rate/40
	2	-2	Not supported	2.0 to 19.2	data_rate/40
	2	-3	Not supported	1.0 to 16.7	data_rate/40
	3	-3	Not supported	2.0 to 16.7	data_rate/40
Agilex™ 7 (E-Tile)	2	-2	Not supported	2.0 to 17.4	data_rate/40
	3	-2	Not supported	2.0 to 17.4	data_rate/40
	3	-3	Not supported	2.0 to 16.0	data_rate/40
Agilex™ 5 E-Series (Device Group B)			Not supported	17.16	data_rate/40
Agilex™ 3 C-Series		-6	Not supported	2.0 to 12.5*	data_rate/40
Agilex™ 3 C-Series		-7	Not supported	2.0 to 12.5*	data_rate/40
Stratix® 10 (L-Tile and H-Tile)	1	1	2.0 to 12.0	2.0 to 16.02	data_rate/40
	1	2	2.0 to 12.0	2.0 to 14.0	data_rate/40
	2	1	2.0 to 9.83	2.0 to 16.02	data_rate/40
	2	2	2.0 to 9.83	2.0 to 14.0	data_rate/40
	3	1	2.0 to 9.83	2.0 to 16.02	data_rate/40
		2	2.0 to 9.83	2.0 to 14.0	data_rate/40
		3	2.0 to 9.83	2.0 to 13.0	data_rate/40
Stratix® 10 (E-Tile)	1	1	Not supported	2.0 to 16.02	data_rate/40
	1	2	Not supported	2.0 to 14.0	data_rate/40
	2	1	Not supported	2.0 to 16.02	data_rate/40
	2	2	Not supported	2.0 to 14.0	data_rate/40
	3	3	Not supported	2.0 to 13.0	data_rate/40
Arria® 10	1	1	2.0 to 12.0	2.0 to 15.0⁽²⁾⁽³⁾	data rate/40
	2	1	2.0 to 12.0	2.0 to 15.0⁽²⁾⁽³⁾	data rate/40
	2	2	2.0 to 9.83	2.0 to 15.0⁽²⁾⁽³⁾	data rate/40
	3	1	2.0 to 12.0	2.0 to 14.2⁽²⁾⁽⁴⁾	data rate/40
	3	2	2.0 to 9.83	2.0 to 14.2⁽²⁾⁽⁵⁾	data rate/40
	4	3	2.0 to 8.83	2.0 to 12.5⁽⁶⁾	data rate/40
Cyclone® 10 GX		-5	2.0 to 9.8	2.0 to 9.8	data rate/40
Cyclone® 10 GX		-6	2.0 to 6.25	2.0 to 9.8	data rate/40

Table 2 - JESD204C FPGA IP Core Performance

Device Family	PMA Speed Grade	FPGA Fabric Speed Grade	Data Rate		Link Clock fMAX (MHz)
			Enable Hard PCS (Gbps)	Enable Soft PCS (Gbps)	Link Clock fMAX (MHz)
Agilex™ 7 (F-Tile)	1	-1	Not supported	5 to 32.44032	data_rate/40
	1	-2	Not supported	5 to 32.44032	data_rate/40
	2	-1	Not supported	5 to 28.8948*	data_rate/40
		-2	Not supported	5 to 28.8948*	data_rate/40
		-3	Not supported	5 to 24.33024	data_rate/40
	3	-3	Not supported	5 to 17.4	data_rate/40
Agilex™ 7 (E-Tile)	1	-1	Not supported	5 to 28.9	data_rate/40
	2	-2	Not supported	5 to 28.3	data_rate/40
	2	-3	Not supported	5 to 25.6	data_rate/40
	3	-2	Not supported	5 to 17.4	data_rate/40
	3	-3	Not supported	5 to 17.4	data_rate/40
Agilex™ 5 E-Series (Device Group B)		-4	Not supported	17.16	data_rate/40
		-5	Not supported	17.16	data_rate/40
		-6	Not supported	17.16	data_rate/40
Agilex™ 5 E-Series (Device Group A) / D-Series		-1	Not supported	28.1	data_rate/40
		-2	Not supported	28.1	data_rate/40
		-3	Not supported	28.1	data_rate/40
Stratix® 10 (E-Tile)	1	-1	Not supported	5 to 28.9	data_rate/40
	1	-2	Not supported	5 to 25.6	data_rate/40
	2	-1	Not supported	5 to 28.3	data_rate/40
	2	-2	Not supported	5 to 25.6	data_rate/40
	3	-1	Not supported	5 to 17.4	data_rate/40
		-2	Not supported	5 to 17.4	data_rate/40
		-3	Not supported	5 to 17.4	data_rate/40

*Maximum data rate may reduce with ECC enable. Please refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information.

1. Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization.

2. Refer to the Arria® 10 and Stratix® 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.

3. When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.

4. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.

5. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.

6. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.

2. Design Flow and IP Integration

IP Integration Information

Topic	Agilex™ 7	Stratix® 10	Arria® 10
Synchronized	AN 967: Multiple Device Synchronization in Digital Phased Array System AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP - Synchronized ADC to Agilex 7 Dual Link	AN804: Implementing Synchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core	AN803: Implementing Synchronized ADC Multi-link Designs with Arria® 10 JESD204B RX IP Core AN 814: Arria® 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design
Unsynchronized		AN804: Implementing Unsynchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core	AN803: Implementing Unsynchronized ADC Multi-link Designs with Arria® 10 JESD204B RX IP Core

3. Board Design and Power Management

Topic	Agilex™ 7	Agilex™ 5	Agilex™ 3	Stratix® 10	Arria® 10	Cyclone® 10	Max® 10
Pin Connection Guidelines	Agilex™ 7 Device Family Pin Connection Guidelines	Agilex™ 5 FPGAs and SoCs Pin Connection Guidelines	Agilex™ 3 FPGAs and SoCs Pin Connection Guidelines	Stratix® 10 GX, MX, TX and SX Device Family Pin Connection Guidelines	Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines	Cyclone® 10 GX Device Family Pin Connection Guidelines	MAX® 10 FPGA Device Family Pin Connection Guidelines
Schematic Review Worksheets	Agilex™ 7 Device Schematic Review Worksheet	Agilex™ 5 Device Schematic Review Worksheet		Stratix® 10 Device Schematic Review Worksheet	Arria® 10 GX, GT, and SX Schematic Review Worksheet	Cyclone® 10 GX Schematic Review Worksheet	MAX® 10 Schematic Review Worksheet
Board Design Guidelines	Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines AN 114: Board Design Guidelines for Programmable Device Packages AN 886: Agilex™ 7 Device Design Guidelines Board Design Guidelines Solutions	Agilex™ 5 FPGAs and SoCs Device Design Guidelines AN 114: Board Design Guidelines for Programmable Device Packages	Agilex™ 3 FPGAs and SoCs Device Design Guidelines	AN 766: Stratix® 10 Devices, High-Speed Signal Interface Layout Design Guideline AN 613: PCB Stackup Design Considerations for FPGAs Board Design Guidelines Solutions	AN 613: PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for Programmable Device Packages Board Design Guidelines Solutions	AN 613: PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for Programmable Device Packages Board Design Guidelines Solutions	AN 613: PCB Stackup Design Considerations for FPGAs AN 114: Board Design Guidelines for Programmable Device Packages Board Design Guidelines Solutions
Power Management	Agilex™ 7 Power Management User Guide AN 910: Agilex™ 7 Power Distribution Network Design Guidelines	Agilex™ 5 FPGAs and SoCs Power Management User Guide	Agilex™ 3 FPGAs and SoCs Power Management User Guide		AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide Early Power Estimator (EPE) and Power Analyzer	AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide Early Power Estimator (EPE) and Power Analyzer	AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide Early Power Estimator (EPE) and Power Analyzer
Thermal Power Management	AN 944: Thermal Modeling for Agilex™ 7 FPGAs			AN 787: Stratix® 10 Thermal Modeling and Management
Power Sequencing	AN 692: Power Sequencing Considerations	AN 692: Power Sequencing Considerations		AN 692: Power Sequencing Considerations	AN 692: Power Sequencing Considerations	AN 692: Power Sequencing Considerations

4. Interoperability and Standards Testing

Topic	Agilex™ 7 JESD204C	Stratix® 10 JESD204B	Stratix® 10 JESD204C	Arria® 10 JESD204B
Interoperability Checkouts Reports	AN 976: Agilex™ 7 F-Tile Devices JESD204C FPGA IP and ADI AD9081 MxFE* DAC AN 960: Agilex™ 7 E-Tile Device JESD204C FPGA IP and ADI AD9081 MxFE* ADC AN 876: Agilex™ F-Tile Devices JESD204C FPGA IP and ADI AD9081 MxFE* ADC	AN 905: Stratix® 10 Devices JESD204B FPGA IP and ADI AD9213 AN 915: Stratix® 10 E-Tile Devices JESD204B FPGA IP and ADI AD9208 AN 890: Stratix® 10 L-Tile Devices JESD204B FPGA IP and ADI AD9174 AN 833: Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200	AN 949: Stratix® 10 E-Tile Devices JESD204C FPGA IP and ADI AD9081 MxFE* DAC AN 916: Stratix® 10 E-Tile Devices JESD204C FPGA IP and ADI AD9081/AD9082 MxFE* AN 909: Stratix® 10 Devices JESD204C FPGA IP and TI ADC12DJ5200RF
Hardware Checkouts Reports		AN 832: Stratix® 10 Devices JESD204B IP Core and ADI AD9208 AN 823: Stratix® 10 L-Tile Devices JESD204B IP Core and ADI AD9625		AN 810: FPGA JESD204B IP Core and ADI AD9208 AN 792: FPGA JESD204B IP Core and ADI AD9371 AN 785: FPGA JESD204B IP Core and ADI AD9162 AN 779: FPGA JESD204B IP Core and ADI AD9691 AN 753: FPGA JESD204B IP Core and ADI AD6676 AN 749: FPGA JESD204B IP Core and ADI AD9144 AN 712: FPGA JESD204B MegaCore Function and ADI AD9625 AN 710: FPGA JESD204B MegaCore Function and ADI AD9680

Topic

Agilex™ 7

JESD204C

Stratix® 10

JESD204B

Stratix® 10

JESD204C

Arria® 10

JESD204B

Interoperability Checkouts Reports

Hardware Checkouts Reports

5. IP and Design Examples User Guides

Table 3: Consolidated JESD204B and JESD204C Resources

Topic	Agilex™ 7 JESD204B	Agilex™ 7 JESD204C	Agilex™ 5 JESD204B	Agilex™ 5 JESD204C	Agilex™ 3 JESD204B	Stratix® 10 JESD204B	Stratix® 10 JESD204C	Cyclone® 10 JESD204B	Arria® 10 JESD204B	Stratix® V JESD204B	Arria® V JESD204B	Cyclone® V JESD204B
IP User Guide	JESD204B FPGA IP F-Tile JESD204B FPGA IP	JESD204C FPGA IP F-Tile JESD204C FPGA IP	GTS JESD204B FPGA IP	GTS JESD204C FPGA IP	GTS JESD204B FPGA IP	JESD204B FPGA IP	JESD204C FPGA IP	JESD204B FPGA IP	JESD204B FPGA IP	JESD204B FPGA IP	JESD204B FPGA IP	JESD204B FPGA IP
Design Examples User Guide	JESD204B Agilex™ FPGA IP F-Tile JESD204B FPGA IP	JESD204C Agilex™ FPGA IP F-Tile JESD204C FPGA IP		GTS JESD204C FPGA IP		JESD204B Stratix® 10 FPGA IP Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200	JESD204C Stratix® 10 FPGA IP	JESD204B Cyclone® 10 GX FPGA IP	JESD204B Arria® 10 FPGA IP JESD204B FPGA IP Quartus® Prime Standard Edition	JESD204B FPGA IP Quartus® Prime Standard Edition	JESD204B FPGA IP Quartus® Prime Standard Edition	JESD204B FPGA IP Quartus® Prime Standard Edition

Topic

Agilex™ 7

JESD204B

Agilex™ 7

JESD204C

Agilex™ 5

JESD204B

Agilex™ 5

JESD204C

Agilex™ 3

JESD204B

Stratix® 10

JESD204B

Stratix® 10

JESD204C

Cyclone® 10

JESD204B

Arria® 10

JESD204B

Stratix® V

JESD204B

Arria® V

JESD204B

Cyclone® V

JESD204B

IP User Guide

GTS JESD204B FPGA IP

GTS JESD204C FPGA IP

GTS JESD204B FPGA IP

JESD204B FPGA IP

JESD204C FPGA IP

JESD204B FPGA IP

JESD204B FPGA IP

JESD204B FPGA IP

JESD204B FPGA IP

JESD204B FPGA IP

Design Examples User Guide

GTS JESD204C FPGA IP

JESD204C Stratix® 10 FPGA IP

JESD204B Cyclone® 10 GX FPGA IP

JESD204B FPGA IP Quartus® Prime Standard Edition

JESD204B FPGA IP Quartus® Prime Standard Edition

JESD204B FPGA IP Quartus® Prime Standard Edition

6. Training Courses and Videos

FPGA Technical Training

Additional Training Videos

Video Title	Description
JESD204B MegaCore IP Overview	This online course provides a broad overview of the JESD204B FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core.

Video Title

Description

JESD204B MegaCore IP Overview

This online course provides a broad overview of the JESD204B FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core.

FPGA Quick Videos

Additional Quick Videos

Video Title	Description
Agilex™ 7 FPGA F-Tile JESD204C Demo Video	The JESD204B/C standards have been supported on several generations of FPGAs. Watch this demo on how JESD204C works on an Agilex™ 7 FPGA.
Arria® 10 interface to ADI 9144 using JESD204B IP	Learn about the interoperability of JESD204B FPGA IP core on the Arria® 10 FPGA with the AD9144 converter from Analog Devices Inc. (ADI).
How to interoperate ADI AD9680 with FPGA JESD204B IP Core on Stratix® V FPGA	Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core.
How to interoperate ADI AD9680 with FPGA JESD204B IP on Stratix® V	Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core.
How to interoperate TI DAC37J84 with FPGA JESD204B MegaCore on Stratix® V FPGA	Learn about the interoperability of JESD204B FPGA IP core on the Stratix® V FPGA with the DAC37J84 converter from Texas Instruments.
JESD204B FPGA IP Quick Start Video	Learn about JESD204B standard and the JESD204B FPGA IP solution. Find out how you can easily create a design example that works on hardware.
JESD204B FPGA IP Demonstration	Learn about the interoperability of JESD204B FPGA IP core on the Arria® V FPGA with the DAC37J84 converter from Texas Instruments.

7. Debug

User Guides

Topic	Agilex™ 7 JESD204B	Agilex™ 5 JESD204C	Stratix® 10 JESD204B	Arria® 10 JESD204B	Cyclone® 10 GX JESD204B	Stratix® V JESD204B	Arria® V JESD204B	Cyclone® V JESD204B
FPGA IP Overview	JESD204B FPGA IP Overview	GTS JESD204C FPGA IP User Guide	JESD204B FPGA IP Overview	JESD204B FPGA IP Overview	JESD204B FPGA IP Overview	JESD204B FPGA IP Overview	JESD204B FPGA IP Overview	JESD204B FPGA IP Overview
IP Core Debug Guidelines	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	Designing with the GTS JESD204C	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core	JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core
Transceiver High-Speed Link Tuning Quick Guide				AN 871: Transceiver High-Speed Link Tuning	AN 871: Transceiver High-Speed Link Tuning
Ethernet Link Inspector			Ethernet Link Inspector User Guide

Intellectual Property (IP) Core Release Notes

Topic	Agilex™ 7 JESD204B	Agilex™ 7 JESD204C	Agilex™ 5 JESD204B	Agilex™ 5 JESD204C	Agilex™ 3 JESD204B	Stratix® 10 JESD204B	Arria® 10 JESD204B	Cyclone® 10 GX JESD204B	Stratix® V JESD204B	Arria® V JESD204B	Cyclone® V JESD204B
FPGA IP	JESD204B FPGA IP Core		JESD204B FPGA IP Core		JESD204B FPGA IP Core	JESD204B FPGA IP Core	JESD204B FPGA IP Core	JESD204B FPGA IP Core	JESD204B FPGA IP Core	JESD204B FPGA IP Core	JESD204B FPGA IP Core
E-Tile	JESD204B FPGA IP	E-Tile JESD204C FPGA IP
F-Tile	JESD204B FPGA IP	JESD204C FPGA IP
GTS				GTS JESD204C FPGA IP

Additional Resources

Topic	Agilex™ 7	Agilex™ 5	Agilex™ 3	Stratix® 10	Cyclone® 10	Cyclone® 10 GX	Arria® 10
E-Tile Transceiver PHY	E-Tile Transceiver PHY			E-Tile Transceiver PHY
F-Tile Architecture	F-tile Architecture and PMA and FEC Direct PHY IP
L-Tile and H-Tile Transceiver PHY				L-Tile and H-Tile Transceiver PHY
PHY Lite for Parallel Interfaces	PHY Lite for Parallel Interfaces FPGA IP	PHY Lite for Parallel Interfaces FPGA IP	PHY Lite for Parallel Interfaces FPGA IP	PHY Lite for Parallel Interfaces FPGA IP		PHY Lite for Parallel Interfaces FPGA IP	PHY Lite for Parallel Interfaces FPGA IP
PHY Transceiver					Cyclone® 10 GX Transceiver PHY		Arria® 10 Transceiver PHY

For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.

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JESD204B and JESD204C IP Core Support Center

Getting Started

1. Device and IP Selection

Table 1 - JESD204B FPGA IP Core Performance

Table 2 - JESD204C FPGA IP Core Performance

2. Design Flow and IP Integration

IP Integration Information

3. Board Design and Power Management

4. Interoperability and Standards Testing

5. IP and Design Examples User Guides

Table 3: Consolidated JESD204B and JESD204C Resources

6. Training Courses and Videos

FPGA Technical Training

FPGA Quick Videos

7. Debug

User Guides

Intellectual Property (IP) Core Release Notes

Additional Resources

Still Have Questions?