Nios® V Processor Developer Center

Nios® V documentation and support for development and debugging embedded processor systems using Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, Cyclone® 10 GX, Cyclone® 10 LP, MAX® 10, Arria® V, Cyclone® V, MAX® V, Cyclone® IV devices. For Agilex™ devices, refer to the dedicated Agilex Software Development journey resources listed below.

1. Prerequisites 2. Getting Started 3. Creating Your Own Project 4. Design Examples 5. Additional Resources

Software Development Journeys for Agilex™ 7, Agilex™ 5, and Agilex™ 3 Devices

Design Hubs provide a Step-by-Step Guided Journeys for standard development flows surfacing the key critical resources and documentation.

Agilex™ 7 Software Development Guided Journey

Agilex™ 5 Software Development Guided Journey

Agilex™ 3 Software Development Guided Journey

1. Prerequisites

1.1 Create My Intel® Account

Create your Intel® account from the Register Intel® Account page.
Your Intel account allows you to file service requests, register for training courses, download software, access resources, and more.

1.2 Design Considerations: Why choose the Nios® V processor?

The Nios® V processor is designed for Altera® FPGA devices and developed based on the RISC-V specification. For more information, such as processor performance benchmark, please refer to the Nios® V Processor Reference Manual.

The following table shows the supported features in Nios® V processors for Quartus® Prime Pro version.

Nios® V Processor	RISC-V ISA	Microarchitecture Features	Enabled with	Supported Altera® FPGA Device
Nios® V/c Compact Microcontroller	RISC-V 32I 32 General Purpose Registers (GPR)	State-machine Replacement Supported with Machine Mode Reset Request Interface Error Correction Code (ECC)	Altera® HAL	Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 GX
Nios® V/m Microcontroller	RISC-V 32I Zicsr 32 General Purpose Registers (GPR) Control and Status Register Debug Module based on "RISC-V Debug Specification 0.13.2"	State-machine Replacement Configurable five pipeline stages Supported with Machine Mode Optional Debug Mode Reset Request Interface Error Correction Code (ECC)	Altera® HAL µC/OS-II RTOS FreeRTOS	Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 GX
Nios® V/g General Purpose Processor	RISC-V 32IMF Zicbom Zicsr Smclic Smcsrind 32 General Purpose Registers (GPR) Multiplication/Division Cache Management Single-Precision Floating-Point Extension Control and Status Register Debug Module based on "RISC-V Debug Specification 0.13.2" Core-Local Interrupt Controller Indirect CSR Access	State-machine Replacement Five pipeline stages Supported with Machine Mode Optional Debug Mode Reset Request Interface Instruction and Data Cache Tightly Coupled Memory Custom Instruction Error Correction Code (ECC) Branch Prediction Lockstep Shadow Register	Altera® HAL µC/OS-II RTOS FreeRTOS	Agilex™ 7 Agilex™ 5 Agilex™ 3 Stratix® 10 Arria® 10 Cyclone® 10 GX

Nios® V Processor

RISC-V ISA

Microarchitecture Features

Enabled with

Supported Altera® FPGA Device

Nios® V/c

Compact Microcontroller

RISC-V 32I

32 General Purpose Registers (GPR)

State-machine Replacement
Supported with Machine Mode
Reset Request Interface
Error Correction Code (ECC)

Altera® HAL

Agilex™ 7
Agilex™ 5
Agilex™ 3
Stratix® 10
Arria® 10
Cyclone® 10 GX

Nios® V/m

Microcontroller

RISC-V 32I Zicsr

32 General Purpose Registers (GPR)
Control and Status Register
Debug Module based on "RISC-V Debug Specification 0.13.2"

State-machine Replacement
Configurable five pipeline stages
Supported with Machine Mode
Optional Debug Mode
Reset Request Interface
Error Correction Code (ECC)

Altera® HAL
µC/OS-II RTOS
FreeRTOS

Agilex™ 7
Agilex™ 5
Agilex™ 3
Stratix® 10
Arria® 10
Cyclone® 10 GX

Nios® V/g

General Purpose Processor

RISC-V 32IMF Zicbom Zicsr Smclic Smcsrind

32 General Purpose Registers (GPR)
Multiplication/Division
Cache Management
Single-Precision Floating-Point Extension
Control and Status Register
Debug Module based on "RISC-V Debug Specification 0.13.2"
Core-Local Interrupt Controller
Indirect CSR Access

State-machine Replacement
Five pipeline stages
Supported with Machine Mode
Optional Debug Mode
Reset Request Interface
Instruction and Data Cache
Tightly Coupled Memory
Custom Instruction
Error Correction Code (ECC)
Branch Prediction
Lockstep
Shadow Register

Altera® HAL
µC/OS-II RTOS
FreeRTOS

Agilex™ 7
Agilex™ 5
Agilex™ 3
Stratix® 10
Arria® 10
Cyclone® 10 GX

The following table shows the supported features in Nios® V processors for Quartus® Prime Standard version.

Nios® V Processor	RISC-V ISA	Microarchitecture Features	Enabled with	Supported Altera® FPGA Device
Nios® V/c Compact Microcontroller	RISC-V 32I 32 General Purpose Registers (GPR)	State-machine Replacement Supported with Machine Mode Reset Request Interface Error Correction Code (ECC)	Altera® HAL	Stratix® V Stratix® IV Arria® 10 Arria® II Arria® V Arria® V GZ Cyclone® V Cyclone® IV Cyclone® 10 LP MAX® 10
Nios® V/m Microcontroller	RISC-V 32I Zicsr 32 General Purpose Registers (GPR) Control and Status Register Debug Module based on "RISC-V Debug Specification 0.13.2"	State-machine Replacement Configurable five pipeline stages Supported with Machine Mode Optional Debug Mode Reset Request Interface Error Correction Code (ECC)	Altera® HAL µC/OS-II RTOS FreeRTOS	Stratix® V Stratix® IV Arria® 10 Arria® II Arria® V Arria® V GZ Cyclone® V Cyclone® IV Cyclone® 10 LP MAX® 10
Nios® V/g General Purpose Processor	RISC-V 32IMF Zicbom Zicsr Smclic Smcsrind 32 General Purpose Registers (GPR) Multiplication/Division Cache Management Single-Precision Floating-Point Extension Control and Status Register Debug Module based on "RISC-V Debug Specification 0.13.2" Core-Local Interrupt Controller Indirect CSR Access	State-machine Replacement Five pipeline stages Supported with Machine Mode Optional Debug Mode Reset Request Interface Instruction and Data Cache Tightly Coupled Memory Custom Instruction Error Correction Code (ECC) Branch Prediction Lockstep Shadow Register	Altera® HAL µC/OS-II RTOS FreeRTOS	Stratix® V Stratix® IV Arria® 10 Arria® II Arria® V Arria® V GZ Cyclone® V Cyclone® IV Cyclone® 10 LP MAX® 10

Nios® V Processor

RISC-V ISA

Microarchitecture Features

Enabled with

Supported Altera® FPGA Device

Nios® V/c

Compact Microcontroller

RISC-V 32I

32 General Purpose Registers (GPR)

State-machine Replacement
Supported with Machine Mode
Reset Request Interface
Error Correction Code (ECC)

Altera® HAL

Stratix® V
Stratix® IV
Arria® 10
Arria® II
Arria® V
Arria® V GZ
Cyclone® V
Cyclone® IV
Cyclone® 10 LP
MAX® 10

Nios® V/m

Microcontroller

RISC-V 32I Zicsr

32 General Purpose Registers (GPR)
Control and Status Register
Debug Module based on "RISC-V Debug Specification 0.13.2"

State-machine Replacement
Configurable five pipeline stages
Supported with Machine Mode
Optional Debug Mode
Reset Request Interface
Error Correction Code (ECC)

Altera® HAL
µC/OS-II RTOS
FreeRTOS

Stratix® V
Stratix® IV
Arria® 10
Arria® II
Arria® V
Arria® V GZ
Cyclone® V
Cyclone® IV
Cyclone® 10 LP
MAX® 10

Nios® V/g

General Purpose Processor

RISC-V 32IMF Zicbom Zicsr Smclic Smcsrind

32 General Purpose Registers (GPR)
Multiplication/Division
Cache Management
Single-Precision Floating-Point Extension
Control and Status Register
Debug Module based on "RISC-V Debug Specification 0.13.2"
Core-Local Interrupt Controller
Indirect CSR Access

State-machine Replacement
Five pipeline stages
Supported with Machine Mode
Optional Debug Mode
Reset Request Interface
Instruction and Data Cache
Tightly Coupled Memory
Custom Instruction
Error Correction Code (ECC)
Branch Prediction
Lockstep
Shadow Register

Altera® HAL
µC/OS-II RTOS
FreeRTOS

Stratix® V
Stratix® IV
Arria® 10
Arria® II
Arria® V
Arria® V GZ
Cyclone® V
Cyclone® IV
Cyclone® 10 LP
MAX® 10

1.3 Which Operating System (OS) should I choose?

Bare-Metal

Bare-metal is an application-based system without the support of any operating system.

The bare-metal approach offers:

Absolute control of hardware
Increased efficiency
Minimal size (both flash and memory footprint)
No dependency on other source codes or libraries
Ease in validation and code coverage analysis.

You may also consider bare-metal development if you:

Do not require multi-task or multi-thread operations
Are performing board bring-up and need to focus on each peripheral individually
Are re-using existing legacy code that is already developed as bare metal

To develop a bare-metal application for the Nios® V processor, you must be familiar with developing runtime capabilities to ensure that your application makes efficient use of the resources available in your CPU subsystem. Examples of what may be required are as follows:

In-depth knowledge of the hardware platform
Developing runtime capabilities to manage the process between the core and the cache subsystem if you want to fully utilize the CPU subsystem, as a typical bare-metal application uses only a single core
Developing capabilities to manage and schedule processes, handle inter-process communications, and synchronize events within your application

If your scheduled project does not allow for the effort it may take to become familiar with the above points, then it is recommended that you consider using other alternatives.

Altera® Hardware Abstraction Layer (HAL) and Real-Time Operating System (RTOS)

Considering the above statements, it often makes sense to use an abstraction layer or an operating system to realize the maximum performance from the Nios® V processor with minimal effort.

The following table shows the traits of Altera® HAL and RTOS.

Criteria	Altera® HAL	RTOS
Key Difference	Altera® HAL is a lightweight embedded runtime environment that provides a simple device driver interface for programs to connect to the underlying Altera® FPGA peripherals. The Altera® HAL application program interface (API) is integrated with the ANSI C standard library.	RTOS is a priority-based system and provides pre-emptive task scheduling to ensure a timely and deterministic response to events or interrupts. High-priority and time-critical threads execute in preference to lower priority threads. Threads in an RTOS have bounded latency. A process or thread executes within a specified time limit.
Application	Ideal for applications that are based around Altera® FPGA peripherals.	Ideal for applications that require very fast and predictable responses.
Resource	Lightweight and requires a small memory footprint.	Lightweight and requires a small memory footprint.
Coding Practice	Adheres to Altera® HAL API library when using the Altera HAL device driver.	Adheres to strict coding policies because the code must continuously perform consistently.
Refer to the Nios® V Processor Software Developer Handbook for the latest information on supported OS types. Additionally, you may refer to µC/OS-II Documentation, FreeRTOS* - Real-time Operating System for Microcontrollers.

2. Getting Started

2.1 Select Target Board

We recommend starting your development on an Altera® FPGA development kit because the Nios® V processor design examples are targeted to run on those boards. Please refer to the Design Consideration section for supported Altera® FPGA devices.

Refer to FPGA Development Kits for a list of available boards.

2.2 Install Development Tools

You will need to install the Quartus® Prime software and the Ashling* RiscFree* IDE for Altera FPGA to start developing a Nios® V processor system. Navigate to the FPGA Software Download Center to install the latest software version.

2.3 Create Your First Nios® V Processor System

The Nios V Embedded Processor Design Handbook introduces you to the system development flow for the Nios® V processor. Together with the Quartus® Prime software and the Ashling* RiscFree* IDE for Altera® FPGAs, you can build a complete solution comprising a hardware system design and a software program that runs on the Nios® V processor and interfaces with the components on the Altera® development boards.

3. Creating Your Own Project

3.1 Project Types

The Nios® V Processor Development Tools comprise of Board Support Package Editor and Ashling* RiscFree* IDE for Altera® FPGA to build Nios® processor-based projects. It manages two different types of projects:

Graphical User Interface (GUI)-based project

The Board Support Package (BSP) Editor provides a GUI interface to create, modify, and generate the BSP for Nios® processor-based projects.
The Ashling* RiscFree* IDE for Altera® FPGA is a thin GUI layer that provides a complete and seamless environment for Nios® V processor C/C++ software development. RiscFree* IDE is based on the popular Eclipse framework and the Eclipse C/C++ development toolkit (CDT) plug-ins. You can accomplish all Nios® V processor software development tasks within RiscFree* IDE for Altera® FPGA, including creating, importing, editing, building, running, debugging, and profiling programs.

Command Line Interface (CLI)-based project

The Nios® V Processor Tools allow you to construct a wide variety of complex embedded software systems using a command-line interface. From this interface, you can create, modify, build, and execute Nios® V processor programs with Nios® V Processor Tools commands typed at a command line or embedded in a script.

Refer to Nios® V Processor Software Developer Handbook and Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGAs User Guide for more information.

The following table compares the differences between the two projects.

Feature	GUI-Based Project	CLI-Based Project
Project source file management	Specify sources automatically, for example, by dragging and dropping into project	Specify sources manually using command arguments
Debugging	Yes	Import project to Ashling* RiscFree* IDE for Altera® FPGA Implement OpenOCD Debugging feature
Integrates with custom shell scripts and tool flows	Adopt open standard Eclipse tool flows	Invoke the command line tools from custom scripts of other tools that you might already use in your development flow Run with Tcl scripts to automate the creation of a board support package (BSP) Use bash scripts to build several projects at once

3.2 Design Flow

The figure below illustrates the general Nios® V processor system development flow.

The Nios® V processor development flow consists of three elements as follows:

System design, involving both hardware and software
Hardware design
Software design

You begin your Nios® V processor development by developing a system concept and performing a system requirements analysis. Next, you create and generate the system in the Platform Designer and produce a Platform Designer file. The Platform Designer file includes Nios® V processor cores and standard components. After system generation, hardware and software flows can be initiated.

For Nios® V processor hardware development, you must:

Select the target FPGA based on system requirements. Refer to Design Considerations section.
Integrate the Platform Designer system with the Quartus® Prime software project.
Assign pin locations.
Configure timing requirements and other design constraints.
After compiling the hardware design, download the .sof file to the target board.

For Nios® V processor software development, you must:

Develop your software with the Nios® V Processor Tools and Ashling* RiscFree* IDE for Altera® FPGA. The Nios® V processor software includes the HAL, peripheral drivers, user C/C++ application codes, and custom libraries.
Download the .elf file to the Nios® V processor system on the target board after building the application and board support package (BSP). The Nios® V processor system is ready for testing and debugging.

If you find that your software does not meet specifications during the test, return to the beginning of the software flow and check the application codes, drivers, and BSP to correct any errors and ensure that the Nios® V processor system executes correctly.

If the hardware does not meet specifications, return to the Platform Designer system define and generation step, and restart both the hardware and software flow. The key file required to generate the application software is the Platform Designer system file. Because this file describes hardware components and connections, you must regenerate this file if you make a hardware change. The system is complete when both the software and hardware meet specifications.

4. Design Examples

There are many design examples available to help you get started with Altera® FPGA products. All examples can be used as a starting point for your own designs, and they are customizable to implement other specific use cases.

The Nios® V Processor FPGA IP offers a selection of simple design examples to help you begin your journey with the Nios® V processor.

Detailed documentation can be found in the “Nios® V Processor Design Example Scripts” from the Nios® V Processor Software Development Handbook.

How to run a Nios® V processor “Hello World” application in Altera HAL, µC/OS-II RTOS, and FreeRTOS?

To learn how to run a Nios® V processor “Hello World” application in Altera HAL, µC/OS-II RTOS, and FreeRTOS, refer to the AN 985: Nios® V Processor Tutorial.

How to run a Nios® V processor “Hello World” application in FreeRTOS?

To learn how to run a Nios® V processor “Hello World” application in FreeRTOS, refer to the Nios® V Processor Software Developer Handbook: Implementing FreeRTOS™ Project for the Nios® V Processor.

How to boot a Nios® V processor application?

To learn how to boot a Nios® V processor application, refer to the “Nios® V Processor Configuration and Booting Solutions” section in the Nios® V Embedded Processor Design Handbook: Nios® V Processor Configuration and Booting Solutions.

How to run a Nios® V processor with MicroC/TCP-IP software package?

To learn how to run a Nios® V processor with MicroC/TCP-IP software package, refer to the “Nios® V Processor - Using the Micro/TCP-IP Stack” section in the Nios® V Embedded Processor Design Handbook: Nios® V Processor - Using the MicroC/TCP-IP Stack.

How to run a Nios® V processor with Remote System Update in SDM-based Devices?

To learn how to run a Nios® V processor with Remote System Update in SDM-based Devices, refer to the “Nios® V Processor RSU Quick Start Guide in SDM-based Devices” section in the Nios® V Embedded Processor Design Handbook: Nios® V Processor RSU Quick Start Guide in SDM-based Devices.

How to run a Nios® V processor with Custom Instruction?

To learn how to run a Nios® V processor with Custom Instruction, refer to the “Nios® V Processor — Using Custom Instruction” section in the Nios® V Embedded Processor Design Handbook: Nios® V Processor — Using Custom Instruction.

5. Additional Resources

5.1 Documentation and Collaterals

The following documentation serves as a primary reference for the Nios® V processor.

Documentation Title	Description
Nios® V Processor Software Developer Handbook	Describes the basic information needed to develop embedded software for the Nios® V processor. The chapters in this handbook describe the Nios® V processor software development environment, the Nios® V Processor Tools that are available, and the process for developing software.
Nios® V Embedded Processor Design Handbook	Complements the primary documentation for embedded system development. It describes how to use the tools effectively, and recommends design styles and practices for developing, debugging, and optimizing embedded systems using Altera-provided tools. The handbook also introduces concepts to new users of Altera's embedded solutions, and helps to increase the design efficiency of an experienced user.
Nios® V Processor Reference Manual	Describes the Nios® V processor from a high-level conceptual description to the low-level details of implementation. The chapters in this handbook describe the Nios® V processor architecture, the programming model, and the instruction set.
Embedded Peripherals IP User Guide	Describes the Altera-provided IP cores that work seamlessly with the Nios® V processor in the Quartus® Prime design software. The IP cores are optimized for Altera® devices and can be easily implemented to reduce design and test time.
Ashling* RiscFree* Integrated Development Environment (IDE) for Altera® FPGA	Describes the latest features in the Ashling* RiscFree* IDE development tools. The user guide provides a detailed explanation along with use cases of the respective features.
AN 977: Nios® V Processor Custom Instruction	Describes the custom instruction implementation in Nios® V processor. This application note introduces the custom instructions feature and guides on how to instantiate it into your system.
AN 978: Nios® V Processor Migration Guide	Describes the migration efforts from Nios® II processor to Nios® V processor. This application note explains the difference in system design (hardware and software design) when performing processor migration.
AN 985: Nios® V Processor Tutorial	Provide a quick start guide to generate, simulate, program, and debug a Nios® V processor system.
Nios® V Processor: Lockstep Implementation	Describe the Nios® V Processor Lockstep feature, which utilizes fRSmartComp technology to implement a smart comparator in register transfer level (RTL). Altera utilizes the Dual-Core Lock Step (DCLS) safety architecture to implement the smart comparator. This approach allows for the integration of the technology into the Nios® V/g processor, allowing for the design of fail-safe applications.
AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers	This application note is a fundamental guide for developing LiteRT for Microcontrollers software in a Nios® V processor system. The example demonstrates a single-digit classification problem, based on the MNIST (Modified National Institute of Standards and Technology) database and LeNet-5 Convolutional Neural Network (CNN) model.

5.2 Demonstration Videos

Video Title	Description
Nios® V Processor for Altera FPGA	Overview on what Nios® V processor has to offer.
Nios® V Processor Portfolio Video	Learn about the Nios® V processor portfolio available in the Quartus® Prime Pro Edition Software version 23.3
Nios® V Processor Design Walkthrough Video	Watch the Hello world Design walkthrough demonstrating how to choose the right Nios® V processor for your application.
Getting Started with Nios® V/m Processor	Learn how to generate and build a simple hello world example design in Platform Designer for the Nios® V/m processor.
Setting Up Open-Source Tools for Nios® V/m	Learn how to download and set up the open-source tools for software development on the Nios® V/m processor.
Software Development on the Nios® V/m Processor	Learn about software development on the Nios® V/m processor using the open-source ecosystem.
Debugging the Nios® V Processor Using the Ashling RiscFree IDE for Altera FPGAs	Learn how to debug the Nios® V processor using the Ashling RiscFree IDE for Altera FPGAs.

5.3 Quick Links

Resource	Description
Nios® V Processor - Altera® FPGA	Get the latest features and updates to explore new possibilities with the Nios® V processor.
Self-Service Licensing Center	You can get the Nios® V/m processor IP license at no cost. Documentation for Altera® FPGA Software Installation and Licensing are available on the page for FPGA Software Installation and Licensing.
Altera® FPGA Support Resources	Provides online technical resources from training classes to design examples to forums that guide you through every step of the design process.
FPGA Knowledge Base	Provides a vast number of support solutions, reference articles, error messages, and troubleshooting guides. It is also fully searchable.
Intel Account	Your Intel account allows you to file a service request to get help on specific topics. You can also use it to register for training classes and access other resources.

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