Jam Standard Test and Programming Language (STAPL) meets the necessary system requirements of in-system programming via an embedded processor, as it offers small file sizes, ease of use, and platform independence. Using Jam STAPL for in-system programming via an embedded processor permits convenient in-field upgrades, easy design prototyping, and fast production. These benefits lengthen the life and enhance the quality and flexibility of end-products. It can also reduce device inventories by eliminating the need to stock and track programmed devices.

How It Works 

Using Jam STAPL for in-system programming via an embedded processor takes place in two stages (as shown in Figure 1). First, the Quartus® II development tool generates the Jam STAPL source code, or Jam File (.jam), then stores it in the system memory. The Jam File contains all information required to program the in-system programmability (ISP)-capable device(s), including the programming algorithm and data needed to upgrade one or more devices.

About the Jam File (.jam)

To program Altera FPGA devices using Jam STAPL, designers must first create a Jam File with the Quartus II development software. It is not necessary to recompile existing designs, because the Quartus II software can create a Jam File from a Programmer Object File (.pof). To store a Jam File in erasable programmable read-only memory (EPROM) or Flash memory, it must be converted first to a Hexadecimal (Altera-format) File (.hex) or a similar programming file. Embedded processor software packages or other utilities can automatically convert a Jam File for EPROM or Flash programming. Similarly, some EPROM programmers support "raw binary" or "absolute binary" formats, which allow the Jam File to be read directly by the programmer without conversion.

Figure 2 describes how to generate a Jam File for in-system programming.

About the Jam Player 

The Jam Player is a C program that parses the Jam File, interprets each Jam STAPL instruction, and reads and writes data to and from the JTAG chain. The variables processed by the Jam Player depend on the initialization list variables present at the time of execution. Because each application has unique requirements, the Jam Player source code can be modified easily.

Figure 3 illustrates the Jam Player source code structure.

Note:

1. TCK, TMS, TDI, and TDO are the JTAG I/O pins.

The main program performs all of the basic functions of the Jam Player without modification. Only the I/O functions must be modified. They are contained in the jamstub.c file, as shown in Figure 3, and include functions which specify addresses to I/O pins, delay routines, operating system-specific functions, and routines for file I/O pins. These functions can be customized by simply editing the jamstub.c file to then compile the source code for use on any platform.

The Jam Player resides permanently in system memory, where it interprets the commands given in the Jam File and generates a binary data stream for device programming. This structure confines all upgrades to the Jam File, and it allows the Jam Player to adapt to any system architecture.

Frequently Asked Questions

• Can I use the Jam™ Standard Test and Programming Language (STAPL) Player or Jam STAPL Byte-Code Player with older versions of Jam Files (.jam) and Jam STAPL Byte-Code Files (.jbc)?
• Why do I get a "Device Programming Failure" error when programming devices using the stand-alone DOS Jam STAPL Player with the ByteBlaster® II download cable but not when using the Quartus® II Programmer?
• When programming devices with the Jam™ standard test and programming language (STAPL) files, how do I set the security bits?

Documentation

• Using Jam STAPL for ISP via an embedded processor chapter of the MAX® II Handbook
• JTAG & In-System programmability chapter of the MAX II Handbook
• AN 95: In-System programmability in MAX® devices

Frequently Asked Questions 

• Can I use the Jam STAPL player or Jam STAPL Byte-Code player with older versions of .jam and .jbc?
• How can I determine the contents of the Jam STAPL Byte-Code file (.jbc)?
• Does the Jam STAPL player and the Jam STAPL Byte-Code player support the MasterBlaster™ download cable?
• Does the Jam STAPL player version 2.3 support the USB-Blaster™ download cable?

JTAG Technologies* provides a full range of in-system programming and PCB testing solutions based on the boundary-scan IEEE Standard 1149.1 and related standards, including IEEE 1532. These solutions cover all development phases, including design support, prototype debug, production, and repair.

PLD Programming Development 

JTAG Technologies* products support programmable logic device (PLD) programming, including the JAM standard programming and test language (STAPL) and Serial Vector File (.svf) formats. As a result, programming capability is available for MAX® II, MAX 7000 and MAX 3000A. Regardless of the device type, brand, or format used, the system presents a common interface to the user, avoiding the proliferation of tools. Rapidly created files perform all device operations on-board, such as erase, blank-check, programming, verification, security fuse programming, and user-code readback.

The JTAG ProVision* development system handles a wide variety of scan-chain configurations, ranging from the simple single-chain structure up to multi-chain, multi-level hierarchical scan architectures. Scan chains of any length are possible, with automatic safe configuring of the board during PLD programming. The software GUI guides you in verifying boundary-scan description language (BSDL) files, testing the board's boundary-scan chain, and performing the programming functions.

Production Support 

JTAG Technologies' PLD programming applications run on a wide variety of fully-compatible hardware controllers in a broad range of operating environments. Interfaces are available for PCI*, PXI, USB, Ethernet, FireWire, ISA, and VXI. The production environment includes:

• Stand-alone PC or workstation versions, with an easy-to-use graphical interface for sequencing operations
• Full integration within an existing production step, such as functional test, by means of dynamic linked library-based (DLL-based) applications
• Support for incorporating PLD programming within the National Instruments LabWindows/CVI, LabVIEW platform or NI TestStand 

JTAG Technologies' tools allow PLD programming to be sequenced with other powerful boundary-scan applications, such as board testing and in-system flash programming. Multiple authorization levels are provided for operators, technicians, and engineers. Production personnel benefit from having quick and easy controls, typically via single-button operation, and execution reports that summarize the results.

The Jam Standard Test and Programming Language (STAPL) is compatible with programmable logic devices (PLDs) that offer in-system programmability (ISP). Jam STAPL is a major step forward in providing a software-level standard for in-system programming. Programming support for Jam STAPL is offered by an ever-growing number of vendors.