The FPGA Power Solutions provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. These resources will help guide you through power consumption considerations when planning system designs, estimating power requirements throughout the entire design flow, and meeting demanding power requirements using converters. The converters feature integrated inductors to deliver an industry-leading combination of high efficiency, small footprint, and low-noise performance.

Get additional support for Agilex™ 7 Board Design Guided Journey, Agilex™ 5 FPGA Board Design Guided Journey, Agilex™ 3 FPGA Board Design Guided Journey, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

Power system design is done in several logical phases:

Choosing a Power Tree

In this phase, a power tree topology is chosen based on the requirements of the device. The requirements of the power supply may not yet be known, but the supply voltage and connection requirements of various devices are available in the Power Management Handbooks, and Pin Connection Guidelines. Any required power supply sequencing and SmartVID usage will impact the power tree topology.

Power Estimation

In this phase, the amount of electrical power required by the various device power supplies is estimated using the Early Power Estimator (EPE) tool or FPGA Power and Thermal Calculator (PTC) and the Quartus® Prime Power Analyzer tool. As the design evolves to the final configuration, the quality and type of information available improve and the estimation becomes more accurate.
The current version of the FPGA PTC supports Agilex™ and Stratix® 10 devices. This tool does not support older devices such as the Arria® 10 and Cyclone® 10 families; use the corresponding Early Power Estimator if you are working with those devices.

Power Optimization

In this phase, the device configuration can be optimized for minimum power. This step can involve the Quartus® software power optimization wizard, the SmartVID feature (in some devices), system cooling decisions, and/or dynamic workload management strategies. This phase may occur several times during the evolution of the system and device design.

Power Generation

In this phase, voltage regulator modules (VRMs) are selected based on the power tree and electrical power estimations. VRM selection is critical to producing high-quality power systems with the minimum number and cost of bypass elements.

Power Distribution

In this phase, the power distribution network (PDN) is designed, producing a list of the required number, value, and quality of bypass capacitors using the PDN tool, power tree, VRMs, electrical power estimations, and board physical geometries.

Power Dissipation and Thermal Considerations

In this phase, thermal power estimations are used to select device cooling solutions. The EPE or PTC assists with the cooling of system designs. The effects of junction temperature on device power generation and device reliability should be considered in this phase.

Designing the Power Tree

• AN 721: Creating an FPGA Power Tree
• AN 692: Power Sequencing Considerations for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10 and Cyclone® 10 GX Devices

Power Estimators and User Guides

Early Power Estimators (EPE) and Power Analyzer

Generation

• AN 583: Designing Power Isolation Filters with Ferrite Beads for FPGAs
• AN 692: Power Sequencing Considerations for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10 and Cyclone® 10 GX Devices
• AN 742: PMBus SmartVID Controller Reference Designs

Distribution

• AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology
• AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
• Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide
• Power Distribution Network

Additional Resources

• Board developer center

General

• Thermal Management
• FPGA Package and Thermal Information

Stratix® 10 Devices

• AN 787: Stratix® 10 Thermal Modeling and Management with the Early Power Estimator

User Guides

General

• Early Power Estimator User Guide
• Device-Specific Power Delivery Network (PDN) Tool 2.0 User Guide

Agilex™ Devices

• Agilex™ 7 Power Management User Guide
• Agilex™ 5 FPGAs and SoCs Power Management User Guide
• Agilex™ 3 FPGAs and SoCs Power Management User Guide
• FPGA Power and Thermal Calculator User Guide

Stratix® 10 Devices

• Stratix® 10 Power Management User Guide
• Early Power Estimator for Stratix® 10 FPGAs User Guide

Arria® 10 Devices

• Early Power Estimator for Arria® 10 FPGAs User Guide

Cyclone® 10 GX Devices

• Early Power Estimator for Cyclone® 10 GX FPGAs User Guide

Cyclone® 10 LP Devices

• Early Power Estimator for Cyclone® 10 LP FPGAs User Guide

MAX® 10 Devices

• MAX® 10 Power Management User Guide

Checklists

• SmartVID Debug Checklist for FPGAs
• Early Power Estimator (EPE) and Power and Thermal Calculator (PTC) Debug Checklist

Design Examples and Reference Designs

• AN 742: PMBus SmartVID Controller Reference Designs

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Agilex™ Devices

Stratix® 10 Devices

Arria® 10 Devices

Cyclone® 10 Devices