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High Performance
Agilex 27 FPGA and SoC
Agilex 27 is engineered to deliver the high-performance fabric and connectivity, maximizing throughput, while delivering power efficiency and protecting system and data integrity at line rate to enable tomorrow’s programmable innovations
Agilex 27 FPGA and SoC
Engineered as one system, Agilex 27 FPGA and SoC combine HyperFlex fabric, high-density DSP, next-generation connectivity, and HyperFlow data network movement. Advanced Arm processing and end-to-end security simplify integration, enabling scalable systems with greater performance per watt that adapt to evolving workloads and requirements.
Architecture Leadership for Next-Generation Systems
Agilex 27 extends the Agilex architecture leadership with 1.8x greater performance/watt, and AI Tensor DSP blocks for the next wave of intelligent systems.
High-Bandwidth Data Movement
As AI, networking, wireless, and embedded systems demand more bandwidth, Agilex 27 enables high-speed data movement with advanced SerDes, next-generation Ethernet and PCIe, HyperFlow data network, and the latest memory standards.
End-to-End Security
Agilex 27 protects critical systems from configuration through operation with hardware root of trust, secure boot, key protection, anti-tamper defenses, and integrated datapath encryption.
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Agilex 27 FPGA & SoC
Agilex 27 unites high-performance fabric, advanced connectivity, and efficient data movement with industry-leading power efficiency for scalable, secure physical and digital AI systems that adapt to evolving requirements.
256 Gb/s SerDes
PCIe 7.0 w/IDE
1.6 TbE w/MACsec
UCIe
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M-Series
Accelerate memory-intensive workloads with in-package memory that reduces data bottlenecks, simplifies system design, and minimizes board footprint.
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Direct RF-Series
Simplify high-performance RF systems with the latest integrated data converters that reduce size, weight, power, and signal-chain latency.
Solutions
Altera FPGAs can be used to implement OLT solutions by leveraging the burst mode capabilities of the transceivers, the DDR5 / LPDDR5 memory interfaces, built-in Ethernet MACs for uplink connections, and the core logic to build optimized, differentiated, and future-proof PON MAC solutions.
The fundamental PON functions may be complemented with functions like integrated Ethernet switch/router functions, search functions like Access Control Lists (ACL) / Longest Prefix Match (LPM), Deep Packet Inspection (DPI), or AI inference.
Key Features
- 50G Asymmetric PON OLT, 25GS MSA, XGS, GPON
- Supports Ethernet MAC clients Supports XGEM frame reassembly upstream per ALLOC-ID. This can either be via external DRAM or internal SRAM for smaller applications.
- Supports LDPC FEC: 25G decoder upstream and 50G/ 25G encoder downstream.
Key Applications
- XGS/GPON Combo PON
- 50G Asymmetric with co-existence with legacy solutions on the same optical distribution network (ODN)
- CoDBA for fronthaul
The next wave of wireless innovation, 6G AI RAN, is already here, and Altera is ready with FPGA-optimized production grade IP such as advanced LDPC, alongside scalable reference designs and hardware-validated solutions. Our AI enhanced demos showcase early 6G implementations, enabling continuous optimization as standards evolve. Fully adaptable, these FPGA-based solutions accelerate your path into AI-driven 6G, reducing risk, lowering costs, and future-proofing your network for the next generation of RAN intelligence.
Key Benefits
• Scalable, validated AI reference designs for 6G development
• Continuous FPGA-based optimization as 6G standards evolve
• Production-grade LDPC IP enabling flexible, high-performance implementations
• Reduced package sizes across all densities
Purpose-built for the layer between the CPU, the XPU and the wire. There is work in the data center that software cannot do fast enough and fixed silicon cannot change fast enough. Agilex 27 runs it in hardware: line-rate packet and storage processing, deterministic latency that holds under load, and memory orchestration beside the accelerator, all reprogrammable as standards move
Network Offload: DPU & AI NIC
Cloud and AI infrastructure providers accelerate networking, storage, and security services without sacrificing performance or flexibility. By moving critical data path functions such as virtual switching, RDMA, traffic processing, security, and infrastructure services into programmable hardware, Agilex 27 reduces CPU overhead, delivers deterministic low-latency performance, and enables more efficient use of compute resources. Its adaptable architecture allows operators to evolve protocols, security functions, and infrastructure services through software-defined hardware acceleration, helping customers deploy new services faster, scale infrastructure more efficiently, and reduce total cost of ownership.
Storage Acceleration
Agilex 27 helps storage providers deliver higher performance, lower latency, and greater infrastructure efficiency by accelerating data movement and storage services directly in hardware. By offloading NVMe-oF processing, compression, encryption, erasure coding, and storage management tasks from host CPUs, Agilex 27 enables more data to be processed with fewer server resources while maintaining predictable performance at scale. Its flexible architecture allows storage platforms to adapt to evolving protocols, security functions, and workload demands without hardware redesign, helping customers increase storage density, improve performance-per-watt, and reduce the total cost of delivering data services
AI Infrastructure
Agilex 27 empowers AI infrastructure providers to build higher-performance, more efficient, and more scalable AI systems by eliminating data movement bottlenecks between compute, memory, storage, and networking. By accelerating memory orchestration, AI networking, and infrastructure services in programmable hardware, Agilex 27 keeps valuable AI accelerators fully utilized, reduces latency, and improves performance-per-watt. Its adaptable architecture enables customers to support rapidly evolving AI models and infrastructure standards without costly hardware redesigns, helping them deploy AI infrastructure faster, scale more efficiently, and lower the total cost of delivering AI services.
Secure communications demand adaptability, reliability, and efficiency under strict SWaP (size, weight, and power) constraints. To address these demands, FPGAs enable software-defined waveforms, advanced signal processing, and low-latency multi-channel data handling.
Strict logic separation ensures encrypted and unencrypted data protection, while hardened cryptographic services, including cryptographic blocks and key management subsystems, provide secure encryption, authentication, and compliance with military standards.
With multiple processors, FPGAs enable independent task operation and reduce SWaP burdens through compact, efficient designs. They incorporate anti-tamper features and resilience in harsh conditions, delivering reliable performance, and making them indispensable for UAVs, naval systems, and other mission-critical applications.
Robotics is moving from isolated, scripted machines to adaptive systems that combine more cameras, LiDAR or radar, IMUs, encoders, industrial I/O, networking, AI inference, and closed-loop control. As robots become more capable, they also need tighter synchronization, faster data movement, safer failure behavior, and more consolidation at the edge.
Agilex 27 combines flexible FPGA fabric with hardened data movement and latest Arm processor system. Capture, process, move, and control can be coordinated as one pipeline: sensor data is timestamped and preprocessed near the input, AI-ready streams move to CPU/GPU inference, and time-critical control and safety stay isolated from changing AI workloads.
Resources
Documentation
Common Questions
Agilex 27 delivers higher usable performance, greater implementation headroom, and improved power efficiency for demanding designs. AI Tensor DSP blocks accelerate compute, while HyperFlow simplifies high-bandwidth data movement and frees FPGA resources for differentiation. Next-generation connectivity, advanced Arm processing, and end-to-end security reduce integration complexity and enable scalable systems that adapt as requirements evolve.
Choose Agilex 27 FPGA or SoC when sustained fabric performance at high utilization, high-speed connectivity, and leading performance per watt are the primary requirements
Choose Memory when high-bandwidth memory in-package and greater data locality are needed to reduce memory bottlenecks, board area, power, or system complexity.
Choose Direct RF when integrated RF data conversion and signal-chain integration are the primary requirements in addition to FPGA and SoC
Agilex 27 devices share a common platform built on 3rd Generation HyperFlex architecture, AI Tensor DSPs, HyperFlow data network, 256 Gb/s SerDes, 1.6TbE, PCIe 7.0, and LPDDR6 plus end-to-end device and data security. SoC options add Cortex-A720/A520 processing. M-Series adds memory in-package; and Direct RF-Series adds integrated RF data conversion vie UCIe chiplets
HyperFlow is a hardened, full-chip data network that combines a system NoC, distributed fabric NoC, and integrated DMA engines to move data efficiently between memory, PCIe, SDM, HPS, and FPGA fabric without consuming programmable logic or routing resources.
Security in Agilex 27 starts at a hardware root of trust and extends through configuration, active data paths, and the full product lifecycle. As cyber threats continue to expand from device compromise to attacks on data, communications, and supply chains, Agilex 27 provides layered protection across the system to help reduce the attack surface and strengthen platform resilience. Dedicated MACsec, PCIe IDE, and external memory IME blocks.
Agilex 27 SoC devices has two high-performance Cortex-A720 and two power-efficient Cortex-A520 cores. Demanding workloads run on the A720 cores, while background tasks run efficiently on the A520 cores. Armv9.2 architecture adds advanced processing, security, and reliability.