Wireless and Commercial Satcom

Altera’s O-RU Macrocell Enablement Package provides production-grade IP, reference designs, and documentation to accelerate development of O-RAN-compliant macrocell O-RUs for Split 7.2 deployments.

Altera’s ‘Olympia Bridge’ workload is an FPGA-based solution for 32T32R - 64T64R O-RU. It is a full O-RAN-compliant pre-production design for O-RAN, Beamforming, and Low PHY designed to accelerate bootstrapping of O-RU Split 7.2 Category B and Category C (ULPI).

The Altera 32T32R 5G NR MIMO O-RU development platform operates in the 3.4–3.8 GHz n78 TDD band and provides low output power (0.25 Watts per antenna) for user testing.

Altera’s ‘Sail River’ workload is an FPGA-based solution for 4T4R – 8T8R O-RU. It is a full O-RAN-compliant preproduction design, including Low PHY and DFE, designed to accelerate bootstrapping of O-RU Split 7.2 Category A deployments.

The Altera 8T8R 5G NR O-RU development platform operates in the 3.47–3.67 GHz n78 TDD band and provides ample power (40 Watts per antenna) for user testing.

Altera’s LDPC-V FEC IP delivers high throughput, low latency, and exceptional performance-per-watt for wireless, optical, cable, and satellite communication systems. Designed for deployment on Agilex® FPGAs and SoC FPGAs, the solution supports today’s 5G, PON, DOCSIS, and NTN infrastructures while providing a scalable path toward future 6G networks.

Agilex® 7 SoC FPGAs deliver power savings and added fabric functionality for 5G beamforming system designs, based on Altera benchmarks.

Agilex FPGAs and SoC FPGAs can dramatically boost the L1 capabilities of ASICs and off-the-shelf CPUs and SoCs, future-proofing and adding intelligence to distributed units in next-generation 6G cellular radio access networks.

The ongoing wave of digitization is amplifying connectivity demands, with mobile wireless standing as the de facto communication standard. As a result, wireless mobile standards must evolve and grow more stringent to meet these market needs.

The Precision Time Protocol (PTP) synchronizes clocks across networked devices to maintain a unified and precise time reference. In systems where components must coordinate actions, such as logging, data exchange, or event triggering, PTP ensures consistent timing, enabling deterministic operations and improving overall system integrity.

This user guide provides the features, architecture description, steps to instantiate, and guidelines to design the F-Tile JESD204C IP using Agilex 7 and Agilex 9 FPGA devices.

This user guide provides the features, usage guidelines, and detailed description for the design examples for the GTS JESD204C IP using Agilex 5 FPGA devices.

The F-Tile Avalon-ST IP for PCI Express Design Example is a simple design to demonstrate the establishment of PCIe connectivity of F-Tile FPGA in Quartus® Prime.

Request Access for Olympia Bridge Complete Radio Design​

Request Access for Sail River Complete Radio Design

These kits deliver maximum bandwidth, advanced transceiver support, high-speed interfaces, and powerful compute resources for your most performance-critical designs.

These kits offer scalable logic, rich I/O options, and efficient processing to support a wide range of feature-rich designs.

Design, compile, and debug Altera FPGAs with Quartus Prime. Use synthesis, timing analysis, and board debug tools to turn RTL into working hardware.

Turn MATLAB and Simulink DSP models into FPGA designs with DSP Builder. Generate pipelined hardware and verify signal-processing results against a model.

Supports AI-driven RAN with production IP and adaptable, validated FPGA signal processing.

Partners: 

• Bigcat Wireless 
• Hitek Systems 
• Syntronic 
• Massive Beams 

Interoperable RFICs: 

• Analog Devices 
• Texas Instruments 
• Maxlinear 
• Broadcom