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FPGA Development Tools & Software
DSP Builder
Turn MATLAB and Simulink DSP models into FPGA designs with DSP Builder. Generate pipelined hardware and verify signal-processing results against a model.
Overview
DSP Builder enables the implementation of DSP designs with high performance and productivity, benefitting applications such as artificial intelligence, RADAR, wireless and wireline communications, medical imaging, and motor control. It supports the Agilex® FPGA device portfolio, Stratix® 10, Arria® 10, and Cyclone® 10 FPGA GX devices.
Benefits
Provides Ease of Use
- Perform push-button design migration to the hardened fixed- and floating-point DSP block in Arria® 10, Stratix® 10, and Agilex® FPGA device families.
- Automatically generate projects and verification scripts for the Quartus® Prime Design Software, Timing Analyzer, Platform Designer, and Questa*-FPGA Edition.
- Generate resource utilization tables for your designs without requiring a Quartus® Prime compile.
Reduces Time to Design Success
- Perform high-level synthesis optimizations, auto-pipeline insertion and balancing, and targeted hardware mapping.
- Use a designer-specified system clock constraint to control the automatic pipelining and time-division multiplex/folding.
- Access highly configurable FFTs, FIRs, and advanced mathematical functions.
- Import RTL into your MathWorks MATLAB/Simulink environment for co-simulation and code generation.
Accelerates Design Verification
DSP Builder enables interactive testbench creation and co-simulation between Simulink and RTL, allowing designers to compare simulation results with generated HDL outputs. This helps identify design issues earlier and increases confidence before FPGA implementation.
Tool Integration
Simulink (Mathworks)
DSP Builder is interoperable with other Simulink blocksets. You can use the basic Simulink blockset to create interactive testbenches which allow you to compare the behavior of your DSP Builder design with a reference result that you provide.
Quartus® Prime Design Software
DSP Builder allows you to build high-speed, high-performance DSP datapaths with automatic pipeline register insertion. You then use the Quartus Prime design software to complete the synthesis and place-and-route process for your target FPGA device.
Platform Designer
DSP Builder creates a conduit interface and component description file (hw.tcl) for each design. DSP Builder creates a memory-mapped interface only if the design contains interface blocks or external memory blocks. DSP Builder can also create an Avalon® Streaming interface. The hw.tcl file can expose the processor bus for connection in Platform Designer.
Questa*-FPGA Edition Software
If the Questa executable is in your path, you can run the Questa simulator from within DSP Builder. The automatic testbench flow generates and runs a test script which allows you to compare Simulink simulation results with the output of the RTL simulator that simulates the generated HDL.
Resources
Training & Learning
Common Questions
Use fixed point when measured precision is sufficient and resource efficiency matters. Choose floating point when dynamic range or accuracy requires it.
Pipelining adds cycles of latency while helping meet clock targets. Align reference-model comparisons with the generated hardware's documented delay.
Match numeric types, rounding, saturation, reset and latency. Use identical test vectors to locate the first divergent pipeline stage.
Use folding when available clock rate exceeds sample throughput needs. Verify latency and resource-sharing constraints against the application.
Generate the component description and required interfaces, then connect control and data paths in Platform Designer.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.