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Mid-Range
Agilex® 5
Mid-range FPGAs and SoCs with AI tensor blocks, high compute density, and optimized performance per watt for edge and embedded designs.
Explore the Agilex 5 Family
Agilex 5 devices bring AI acceleration, efficient programmable logic, high-speed connectivity, advanced memory interfaces, and multi-core Arm® processing to mid-range applications. Choose the compact, power-optimized E-Series or scale to the higher-density D-Series for more compute, transceivers, and hardened connectivity.
AI Built Into the Fabric
AI tensor blocks deliver higher compute density for inference and signal-processing workloads without adding a separate accelerator.
Performance per Watt for the Mid-Range
Intel® 7 process technology and second-generation Hyperflex® architecture help reduce total power while improving performance for edge and mid-range designs.
Scale From Compact Edge to High-Density Systems
Two series span compact packages and lower logic densities through larger devices with more transceivers, memory bandwidth, and hardened IP.
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Agilex 5 E-Series
Optimized for power and size - ideal for intelligent edge, embedded, and other compact applications.
- 50K-656K logic elements
- Packages as small as 15 mm × 15 mm
- Up to 24 × 28G transceivers
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Agilex 5 D-Series
Optimized for performance and power efficiency across compute-intensive applications and markets.
- 515K-1,616K logic elements
- Packages as small as 32 mm × 32 mm
- Up to 48 × 28G transceivers
Compare Series
| Feature | E- Series | D- Series |
|---|---|---|
| Logic Elements | 50K-656K | 515K-1,616K |
| Package as small as | 15 mm x 15 mm | 32 mm x 32 mm |
| Max Transceiver Count / Rate | 24 / 28 Gbps | 48 / 28 Gbps |
| Interfaces | up to PCIe 4.0 x4 and 10/25GbE x6 Hard IP | up to 6 PCIe 4.0 x8 and 24 x 10/25GbE Hard IP |
| Memory Interfaces | DDR4 to 2,667; DDR5 to 3,600; LPDDR4/5 to 3,733 Mbps | DDR5 to 5,600; LPDDR5 to 5,500; DDR4 to 3,200; LPDDR4 to 4,267 Mbps |
| DSP Compute | Peak TOPS INT8 up to 26 | Peak TOPS INT8 up to 152.6 |
| 18x19 Multipliers | up to 1,692 | up to 9,936 |
| Processor (SoC Option) | Multi-core Arm Cortex-A55 @ 1.5 GHz and Cortex-A76 @ 1.8 GHz | Multi-core Arm Cortex-A55 @ 1.5 GHz and Cortex-A76 @ 1.8 GHz |
| MIPI D-PHY (v2.5) | up to 3.5 Gbps per lane | up to 3.5 Gbps per lane |
Solutions
Agilex 5 FPGAs and SoC FPGAs give industrial and robotics teams one adaptable platform for deterministic control, multi-axis motor control, sensor fusion, machine vision, and AI inference. Integrated AI tensor blocks can accelerate inspection, classification, and other edge-intelligence workloads, while programmable logic handles time-critical I/O and control functions in parallel. Compact package options, Arm processor-based SoC variants, and high-speed connectivity help consolidate system functions, reduce board complexity, and adapt equipment as interfaces, algorithms, and automation requirements evolve.
Agilex 5 devices provide a reprogrammable processing and connectivity platform for broadcast and Pro AV equipment, including cameras, production switchers, converters, displays, and video-over-IP endpoints. Parallel DSP resources and AI tensor blocks can support low-latency image enhancement, scaling, analysis, and format conversion, while 28G transceivers and hardened Ethernet and PCIe connectivity move high-bandwidth media streams efficiently. Designers can update interfaces and processing pipelines as resolutions, codecs, transport standards, and production workflows change.
Agilex 5 devices can accelerate the acquisition, filtering, reconstruction, and analysis pipelines used in medical imaging, diagnostic systems, laboratory instruments, and test and measurement equipment. Programmable logic supports deterministic, low-latency data movement and custom sensor or converter interfaces, while DSP resources and AI tensor blocks provide hardware acceleration for signal, image, and inference workloads. Arm processor-based SoC options and reconfigurable I/O allow teams to integrate control and application software and update algorithms, interfaces, and instrument capabilities over a long product lifecycle.
Agilex 5 devices combine programmable packet processing, signal processing, and high-speed connectivity for wireless and wireline infrastructure at the network edge. Reconfigurable logic can implement timing-sensitive fronthaul, backhaul, transport, security, and traffic-management data paths, while DSP and AI resources accelerate compute-heavy functions without requiring a separate device. Up to 28G transceivers, hardened Ethernet and PCIe interfaces, power-efficient mid-range density, and SoC processor options help equipment vendors support changing protocols, bandwidth targets, and deployment requirements on a common platform.
Start Design
Start your Agilex 5 design. Choose a development path below to find the right documentation, tools, boards, examples, and step-by-step guidance.
Agilex 5 FPGA E-Series 065B Premium Development Kit
This Dev Kit integrates a wide array of connectivity options including dual QSFP and SFP+ ports, PCIe Gen4 via FMC+, USB 3.1, and multiple Ethernet interfaces and features the A5E065BB32AEA device (Group B).
Altera Agilex 5 Development Kits
See all DEV Kits offered by Altera for Agilex 5.
All Agilex 5 Boards
See all DEV Kits offered by Altera and our Partners for Agilex 5.
Demo Videos
Agilex 5 TinyML Demo with FPGA AI Suite Video
Watch the AI capabilities of Agilex 5 devices with tensor blocks and soft processors.
Agilex 5 SoC FPGA Robotics Demo Video
Watch the Agilex 5 SoC FPGA integrate in real-time with a ROS 2-based Robot Controller.
Agilex 5 FPGAs In-Action Hard Processor System Demo Video
Watch the powerful Arm* Cortex* processors booting up the Linux* OS on Agilex 5 FPGA E-Series devices.
Resources
Documentation, downloads, videos, training, and support for Agilex 7.
Common Questions
Choose E-Series for suitable power and footprint targets. Choose D-Series when its greater density, memory or connectivity resources are needed
Arm cores execute software while FPGA logic handles custom parallel processing. Partition work according to latency, throughput and data-movement requirements.
Compare supported speed, capacity, power and layout requirements for the exact device. Memory interface rate alone does not determine application bandwidth.
Use current device documentation and the matching software release, then verify arithmetic precision and benchmark conditions before comparing claims
Plan it whenever software depends on FPGA peripherals. Verify boot stages, fabric configuration and bridge availability as a combined system.
Processor and FPGA integration can combine software orchestration with real-time sensor and control pipelines. Validate end-to-end timing requirements,