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Agilex® 5 D-Series
High performance, low power, and small form factors for mid-range applications, with AI Tensor Blocks and DDR5 memory support.
Optimized for Performance and Power Efficiency
D-Series devices deliver high performance, low power, and small form factors for mid-range applications. An industry-leading fabric with AI Tensor Blocks expands logic density to 1.6 million logic elements and raises external DDR5 and LPDDR5 bandwidth, suiting AI edge inference and 4K and 8K video processing.
Up to
2X
better performance per watt versus 7 nm node competitors
Up to
42%
lower total power consumption versus Stratix® 10 FPGAs
Up to
1.5X
fabric performance compared to Stratix 10 FPGAs
Benefits
Built for Performance and Power Efficiency
An industry-leading fabric architecture integrated with AI Tensor Blocks expands logic density up to 1.6 million logic elements and increases external DDR5 and LPDDR5 memory bandwidth up to 5,600 Mbps and 5,500 Mbps, for mid-range workloads such as AI edge inference and 4K and 8K video processing.
Security and Reliability
The Secure Device Manager offers advanced security features including post-quantum cryptography native boot, bitstream encryption and authentication, physically unclonable function key storage, and physical anti-tamper protection.
Accelerate with AI
Accelerate AI workloads with the industry's first FPGAs integrating Enhanced DSP with AI Tensor Blocks, and create custom-sized inference IP through a single push-button flow that incorporates standard AI frameworks.
Specifications
Enhanced DSP with AI Tensor Block
Offers up to 152.6 peak INT8 TOPS with FPGA AI Suite support to enable push-button flow from industry standard frameworks to FPGA bitstream.
External Memory Interface
Support up to 5,600 Mbps DDR5, 5,500 Mbps LPDDR5, 3,200 Mbps DDR4, 4,267 Mbps LPDDR4.
Transceivers
Support data rates up to 28 Gbps per channel, integrate Hard IP support for up to 6 PCIe 4.0 x8, 24 x 10/25GbE MAC, PCS, FEC, reducing design time and on-chip resources required.
Product Package & Combination Selector
Start Design
Start an Agilex 5 D-Series design with partner boards, production design software, validated connectivity and memory IP, example designs, and guided design journeys for architecture, board, interface, application, AI, and software development.
GTS Ethernet Hard IP
Supports 10GE and 25GE on Agilex 5 for applications across the edge and core, including wireless and wireline communications, video and broadcast equipment, industrial systems, test and measurement, medical electronics, data center, and defense.
5G LDPC FPGA IP
Low-density parity-check codes are linear error-correcting codes that support reliable transmission and reception over noisy channels.
DDR5, DDR4, LPDDR5, and LPDDR4 External Memory Interfaces FPGA IP
Connect external memory with hardened controllers at the rates listed in the specifications section, for faster data processing and more efficient power use.
PCI Express FPGA IP
Implement PCIe 4.0 endpoints and root ports using the hardened controllers available on D-Series devices.
Example Designs for Agilex 5
Find example designs, documentation, and software tools that shorten bring-up and reduce time to production.
Solutions
Run demanding edge inference with up to 152.6 peak INT8 TOPS from Enhanced DSP with AI Tensor Blocks, fed by DDR5 and LPDDR5 bandwidth and a push-button flow from standard frameworks.
Integrate real-time control, machine vision, robotics, and networking with deterministic processing, hardened Ethernet, and advanced device security.
Process high-resolution imaging and sensor data with parallel DSP, large memory bandwidth, and long product lifecycles suited to regulated equipment.
Build radio-access and fronthaul equipment with 5G LDPC IP, deterministic DSP, 28 Gbps transceivers, and hardened 10/25GbE connectivity.
Capture, process, and stream instrument data with high memory bandwidth, PCIe 4.0 host attach, and reconfigurable acquisition paths.
Accelerate packet processing and transport at the edge and in access equipment with hardened 10/25GbE MAC, PCS, and FEC.
Process and transport 4K and 8K media with parallel DSP, video and vision IP, and high external memory bandwidth.
Protect designs and data with post-quantum cryptography native boot, bitstream authentication, PUF key storage, and physical anti-tamper protection.
Demo Videos
Agilex 5 TinyML Demo with FPGA AI Suite Video
Watch the AI capabilities of Agilex 5 devices with tensor blocks and soft processors.
Agilex 5 SoC FPGA Robotics Demo Video
Watch the Agilex 5 SoC FPGA integrate in real-time with a ROS 2-based Robot Controller.
Agilex 5 FPGAs In-Action Hard Processor System Demo Video
Watch the powerful Arm* Cortex* processors booting up the Linux* OS on Agilex 5 FPGA E-Series devices.
Resources
Documentation, downloads, training, and support for Agilex 5.
Training and Learning
Common Questions
Choose D-Series when the supported model needs additional compute, memory bandwidth or logic density. Measure total power and latency for both options
Calculate read/write traffic including buffering and protocol overhead, then compare achievable interface bandwidth and contention with the processing rate.
Peak TOPS reflects arithmetic capacity. Sustained performance also depends on model structure, memory movement, precision and host overhead.
Map lane counts, hard-IP requirements and package restrictions to the exact device before floorplanning and board layout.
Check the installed Quartus release and device package against the documented support milestone for the selected part.
Its compute and memory resources can support parallel video stages. Budget frame buffering, interface traffic and pixel throughput before device selection.
Ready to Order
Confirm the device, logic density, transceiver count, package, speed grade, temperature range, SoC option, and lifecycle requirements in the current D-Series product table. Then contact an authorized distributor or an Altera representative for availability and purchasing support.
Supporting link: View the D-Series Product Table