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Agilex® 5 E-Series
Scalable performance and AI acceleration in a compact, power-efficient footprint, with an asymmetric Arm processor cluster.
Optimized for Power and Size
E-Series devices are optimized for power and size, for intelligent applications at the edge and in embedded systems. A density range from 50K to 656K logic elements, an asymmetric Arm application processor cluster, and AI Tensor Blocks scale from compact sensor designs to demanding edge inference.
Up to
1.6X
Better performance per watt versus 16 nm node competitors
Up to
50%
Lower total power consumption versus Cyclone® V FPGAs
Up to
2.5X
Fabric performance compared to Cyclone V FPGAs
Benefits
Power-Efficient Performance
Agilex 5 E-Series FPGAs deliver superior power-efficient performance at 1.6x better performance per watt compared with competing 16 nm FPGAs, and include the first asymmetric Arm application processor cluster for better HPS energy efficiency.
Unmatched Reliability
Implement reliable and secure systems with functional safety support and an integrated Secure Device Manager offering advanced security features, backed by manufacturing capacity for supply resiliency and predictable lead times.
Innovative, Scalable, and Adaptable
Meet diverse application needs with a broad set of IP and connectivity options across a 50K to 656K logic element density range, supporting the variety of I/O standards found in edge and embedded sensor designs.
Specifications
FPGA Architecture
Advantages include higher throughput, improved power efficiency, greater design functionality, and increased designer productivity.
Enhanced DSP with AI Tensor Block
Offers up to 56 peak INT8 TOPS with FPGA AI Suite support to enable push-button flow from industry standard frameworks to FPGA bitstream.
Advanced Security
Built with robust security features, the Secure Device Manager (SDM) and firmware ensure the confidentiality and integrity of the device.
Product Package & Combination Selector
Start Design
Start an Agilex 5 E-Series design with premium, modular, and compact development kits, production design software, validated IP, example designs, and guided design journeys for architecture, board, interface, application, AI, and software development.
Agilex 5 FPGA and SoC E-Series Development Kit (Premium)
A complete platform for embedded and edge system development, with dual QSFP and SFP28 ports, PCIe via FMC+, USB 3.1, multiple Ethernet interfaces, and DDR4 and LPDDR4 memory.
Agilex 5 FPGA and SoC E-Series Development Kit (Modular)
A modular board and carrier pairing that supports PCIe Gen4, SFP28, HDMI 2.1, DisplayPort 2.0, dual 2.5G TSN Ethernet, and three DDR4 banks for flexible embedded and edge development.
Agilex 5 FPGA E-Series 013B Development Kit
A compact platform for evaluating smaller E-Series devices, with dual LPDDR4 banks, DisplayPort 1.4, dual MIPI, and expansion headers for Raspberry Pi HATs and Pmod modules.
Partner Boards
Find production and evaluation boards for Agilex 5 E-Series devices from Altera partners when a reference kit does not match the target form factor.
Nios V Processors
RISC-V based soft processor IP that scales from simple embedded control to complex, high-performance applications alongside the hardened processor system.
DDR5, DDR4, LPDDR5, and LPDDR4 External Memory Interfaces FPGA IP
Connect external memory with hardened controllers for faster data processing and more efficient power use across edge, networking, and cloud designs.
GTS Ethernet Hard IP
Implement 10GE and 25GE links on Agilex 5 for industrial, video, test, medical, and communications equipment.
Video and Vision Processing Suite
IP functions that speed development of custom video and image processing designs for embedded vision and display applications.
Example Design Hub
Find example designs, documentation, and software tools that shorten bring-up and reduce time to production.
Quartus Prime Pro Edition Design Software
Compile, place and route, verify timing, and program Agilex 5 E-Series FPGA and SoC designs.
FPGA AI Suite
Build and deploy AI inference pipelines that use the Enhanced DSP with AI Tensor Block, with a push-button flow from industry-standard frameworks to bitstream.
Ashling RISCFree IDE
Develop and debug software for Nios V and hardened processor systems in E-Series SoC designs.
Solutions
Run edge inference in a compact power envelope with Enhanced DSP and AI Tensor Blocks delivering up to 56 peak INT8 TOPS, and a push-button flow from standard frameworks to bitstream.
Integrate real-time control, machine vision, robotics, and networking on one power-efficient device, with functional safety support and an integrated Arm processor cluster.
Process imaging and sensor data at the point of care with low power, flexible I/O, functional safety support, and long product lifecycles suited to regulated equipment.
Build compact radio-access, fronthaul, and edge networking equipment with adaptable interfaces and deterministic processing in a small thermal budget.
Capture, process, and stream instrument data with flexible I/O standards and a density range that scales from handheld to benchtop equipment.
Fuse sensors, run real-time control loops, and host ROS-based software on a single SoC FPGA with deterministic latency.
Process and transport high-resolution media with video and vision IP, DisplayPort and MIPI interfaces, and adaptable format support.
Support in-vehicle networking, sensor interfacing, and software-defined platforms with functional safety support and a compact footprint.
Resources
Documentation, downloads, training, and support for Agilex 5.
Common Questions
Reassess processor architecture, boot artifacts, drivers and peripheral interfaces. Rebuild and validate the software against the E-Series hardware design.
Use the supported OS and multiprocessing configuration, then allocate work according to performance and real-time requirements. Verify shared-memory interactions.
Check package-specific pins, lanes and memory interfaces before selecting the smallest footprint. Validate the full I/O assignment in Quartus.
Consult device safety documentation and assess required diagnostics at system level. Device features alone do not establish application compliance.
Check fabric programming, bridge setup, address mapping, clocks and resets, then compare software addresses with the hardware design.
Integrated processing and FPGA pipelines can combine control and image processing. Evaluate bandwidth, latency and thermal needs for the selected modality,
Ready to Order
Confirm the device, logic density, transceiver count, package, speed grade, temperature range, SoC option, and lifecycle requirements in the current D-Series product table. Then contact an authorized distributor or an Altera representative for availability and purchasing support.
Supporting link: View the D-Series Product Table