Quartus^® Prime Design Software

Fitter (Place and Route)

The Compiler's Fitter performs design placement and routing. During place and route, the Fitter determines the best placement and routing of logic in the target FPGA device.

Register Retiming

Register Retiming can balance register chains by retiming (moving) ALM registers into Hyper-Registers in the routing fabric.

Design Partition Planner

A design partition is a logical, named, hierarchical boundary that you can assign to an instance in your design. Defining a design partition allows you to optimize and lock down the compilation results for individual blocks.

Chip Planner

Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter.

Interface Planner

The Interface Planner explores a device's peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legality checks in real-time.

Logic Lock Regions

A Logic Lock region is a powerful type of logic placement and routing constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region, and then assign design nodes and other properties to the region.

Multiprocessor Support (Faster Compile Time)

Using multi-processors for compilation can result in faster compile times depending on the number of cores used.

IP Base Suite

Altera provides full production licenses for some of its popular IP cores in the Altera FPGA IP Base Suite, which is free with the Quartus Prime Software and Quartus Prime Pro Edition Software.

Timing Analyzer

The Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design using an industry-standard constraint, analysis, and reporting methodology.

Design Space
Explorer II

The Design Space Explorer II tool allows you to find optimal project settings for resource, performance, or power optimization goals.

Power Analysis

Power analysis features include Early Power Estimators, Altera® FPGA Power and Thermal Calculator, and the Power Analyzer that give you the ability to estimate power consumption.

Signal Tap Logic Analyzer

The Signal Tap logic analyzer captures and displays the real-time signal behavior in an FPGA design allowing you to probe and debug the behavior of internal signals during normal device operation, without requiring extra I/O pins or external lab equipment.

Transceiver Toolkit

Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time.

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Questa*-FPGA Edition Software

Questa*-FPGA software editions are a version of the Siemens EDA Questa* Core software targeted for Altera® FPGAs devices.

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