Transceiver Toolkit

Q: How does a developer debug software before the SoC FPGA operating system boots?

Use a supported bare-metal debug connection with the correct processor setup and symbols. Follow the device-specific boot and attach sequence.

Q: How does an engineer investigate a multicore HPS application that hangs?

Inspect each core's execution state, synchronization and shared-memory behavior. Check interrupts and peripheral access alongside software locks.

Q: What is required for useful Streamline profiling on a SoC FPGA?

Use a supported target setup and profiling data collection configuration. Match symbols and workload conditions to the executable under investigation.

Q: How does a developer fix incorrect source lines during Arm DS debugging?

Load symbols matching the running binary and correct source mappings. Confirm compiler optimization and rebuilt artifacts before interpreting stepping behavior.

Software and Tools

Accelerate transceiver design and debugging with powerful tools for real-time analysis, testing, and optimization.

Quartus Prime Design Software

Overview

Transceiver Toolkit uses System Console technology to help FPGA and board designers validate transceiver link signal integrity in real-time in a system and improve board bring-up time. Test for bit-error rate (BER) while running multiple links at your target data rate to validate your board design with the Transceiver Toolkit. Tune transceiver analog settings for optimal link performance while using different test metrics to quantify results. Simultaneously test multiple devices across one or more boards using link tests in the Transceiver Toolkit GUI. Support for Agilex^® 3, Agilex 5, Agilex 7, Stratix^® 10, and Stratix V FPGAs and includes adaptive equalization (AEQ) and decision feedback equalization (DFE) for signal transmission robustness.

Quartus Prime Design Software

Key Features

Real-Time Transceiver Tuning	Adjust and monitor transceiver settings live to accelerate board bring-up and debug.
Integrated Bit Error Rate Testing (BERT)	Built-in PRBS generator and checker streamline high-speed link validation.
Eye Viewer with AutoSweep Mode	Automatically scan PMA analog settings while capturing signal eye diagrams for optimal tuning.
Multi-Channel Monitoring & Control	Channel Manager interface enables simultaneous testing and visibility across multiple links or boards.
Signal Integrity Feature Access	Leverage advanced EQ features like Adaptive Equalization (AEQ) and Decision Feedback Equalization (DFE) directly from the toolkit.
Manual Control & Data Logging	Easily manage test plots, manually adjust PMA settings, and compare results with save-and-load tools.

Quartus Prime Pro

Get Started with Transceiver Toolkit included in Quartus Prime Pro Edition Software

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Quartus Prime Standard

Get Started with Transceiver Toolkit included in Quartus Prime Standard Edition Software

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Common Questions

When should Arm Development Studio be chosen over RiscFree for Arm HPS software?

Choose according to supported processor, release and required debug, trace or profiling features. Verify licensing and probe compatibility before committing.

How does a developer debug software before the SoC FPGA operating system boots?

How does an engineer investigate a multicore HPS application that hangs?

What is required for useful Streamline profiling on a SoC FPGA?

How does a developer fix incorrect source lines during Arm DS debugging?

Transceiver Toolkit

Overview

Key Features

Quartus Prime Pro

Quartus Prime Standard

Common Questions