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Wireless
6G AI RAN
FPGA-optimized production-grade IP for AI-driven 6G RAN development.
AI-Driven 6G, Today
The next wave of wireless innovation, 6G AI RAN, is already here. Altera FPGAs deliver production-grade IP such as advanced LDPC, alongside scalable reference designs and hardware-validated AI-enhanced demos for early 6G implementations.
Fully adaptable FPGA-based solutions accelerate the path into AI-driven 6G, reducing risk, lowering costs, and future-proofing networks for next-generation RAN intelligence, with continuous optimization possible as 3GPP standards evolve.
The Challenges, and Why FPGA
The Challenge
Fluid 6G Standards
3GPP 6G standards are still evolving, making fixed-function silicon a risk.
Why FPGA
Bitstream, Not Tape-Out
New splits, bands, algorithms, and security land as a bitstream update.
The Challenge
Power per Watt Constraints
6G RAN demands more signal processing per watt than any prior generation.
Why FPGA
Agilex 7 for FEC & AI/ML
High-performance FEC and AI/ML acceleration fit fixed power and thermal budgets.
The Challenge
Fragmented Functional Splits
OEMs face fragmented functional splits and spectrum plans across deployments.
Why FPGA
Production-Grade LDPC IP
Scalable reference designs adapt across functional splits and spectrum plans.
Why Altera
AI Advanced Holdover
AI replaces costly OCXOs with TCXOs, enabling 30-50% oscillator BOM savings.
AI Digital Pre-Distortion
AI-enhanced DPD improves power amplifier efficiency and linearity, cutting OPEX.
AI CSI Compression
Compresses channel state information up to 10x while preserving accuracy.
AI Channel Estimation
Reduces DSP blocks by 67% and M20K use by 58% at the same throughput.
Get Started
More Wireless Applications
O-RAN Macro RU Enablement
Scales macro/micro radios with validated IP, flexible designs, and field upgrades.
O-RAN mMIMO RU Enablement
Enables efficient beamforming and scalable, field-upgradeable O-RU designs.
Satellite Communications
Brings low-latency processing and reusable 5G IP to satellite and NTN systems.
Common Questions
6G AI RAN development combines evolving radio-access requirements with AI-enhanced signal processing. FPGAs provide adaptable hardware for FEC and selected AI/ML functions, with production-grade IP, scalable reference designs and hardware-validated demonstrations supporting early evaluation as standards and deployment requirements evolve.
Programmable hardware lets supported signal-processing and interface functions change through a new FPGA configuration. This flexibility helps engineers adapt algorithms, functional splits and spectrum plans, with each update still evaluated against the selected device’s resources and the radio system’s power, thermal and performance requirements.
LDPC IP supplies forward-error-correction processing as a reusable FPGA building block. The listed 5G LDPC-V resource supports evaluation alongside AI-enhanced and other radio functions, helping engineers explore adaptable bit-processing architectures while keeping the implemented coding requirements aligned with the evolving RAN design. Explore FPGA LDPC forward-error-correction IP
AI-enhanced functions include advanced holdover, digital pre-distortion, channel-state-information compression and channel estimation. These demonstrations target oscillator cost, amplifier efficiency and linearity, data compression and FPGA resource use, with the reported improvements evaluated for the specific implementation rather than assumed for every RAN platform.
Check the function’s FPGA resource use, throughput, power and thermal fit for the selected RAN implementation. Agilex resources support FEC and AI/ML processing, but demonstration results for CSI compression or channel estimation do not establish the same savings or performance for every radio workload.