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High-Performance
Agilex® 7
High-performance FPGAs and SoCs with up to 116 Gbps transceivers, PCIe 5.0, CXL, and HBM2e for compute- and bandwidth-intensive designs.
Explore the Agilex 7 Family
Agilex 7 FPGAs and SoC FPGAs deliver high fabric and I/O performance for data center, networking, broadcast, defense, and industrial systems. The portfolio spans balanced F-Series devices, bandwidth-focused I-Series devices, and memory-intensive M-Series devices with HBM2e options, plus Arm-based SoC variants.
High Performance per Watt
Second-generation Hyperflex architecture and Intel 10 nm process technology deliver high fabric performance for demanding systems while improving power efficiency.
Up to 116 Gbps Connectivity
Advanced transceiver tiles, PCIe 5.0, CXL, and hardened interfaces support high-bandwidth processor, network, storage, and media connections.
Memory and Compute at Scale
M-Series devices add DDR5, LPDDR5, and up to 32 GB of HBM2e for memory-intensive acceleration, analytics, and data-movement workloads.
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Agilex 7 F-Series
Balances power and performance across a wide range of high-performance FPGA and SoC applications
- 573K-2.7M logic elements
- Up to 58 Gbps transceivers
- PCIe 4.0 x16 and DDR4 support
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Agilex 7 I-Series
Targets processor-interface and bandwidth-intensive applications with the portfolio's fastest transceivers and advanced host connectivity.
- 1.9M-4M logic elements
- Up to 116 Gbps transceivers
- PCIe 5.0 x16 and CXL support
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Agilex 7 M-Series
Targets compute- and memory-intensive acceleration with high-bandwidth external memory and integrated HBM2e options.
- 3.2M-3.8M logic elements
- Up to 116 Gbps transceivers
- DDR5, LPDDR5, and 16 GB or 32 GB HBM support
Compare Series
| Feature | F-Series | I-Series | M-Series |
|---|---|---|---|
| Logic Elements | 573K-2.7M | 1.9M-4M | 3.2M-3.8M |
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Max Transceiver Rate
Maximum transceiver data rate per channel supported by each series. |
Up to 58 Gbps | Up to 116 Gbps | Up to 116 Gbps |
| PCIe | PCIe 4.0 x16 | PCIe 5.0 x16 | PCIe 5.0 x16 |
| Memory Interfaces | DDR4 | DDR4 | DDR4, DDR5, LPDDR5 |
| Processor (SoC Option) | Quad-core Arm Cortex-A53 option | Quad-core Arm Cortex-A53 option | Quad-core Arm Cortex-A53 option |
| Compute Express Link (CXL) Support | - | CXL to Intel® Xeon® Scalable processor | CXL to Intel® Xeon® Scalable processor |
| HBM2e | - | - | 16 GB or 32 GB |
Start Design
Start your Agilex 7 design. Choose a development path below to find documentation, tools, boards, examples, and step-by-step guidance for F-Series, I-Series, and M-Series devices.
System Architecture and Planning
The interactive journey helps you navigate the system architecture & planning phase of your design using the Agilex 7 FPGA devices.
FPGA Board Design
The interactive FPGA Board Guided Journey provides step-by-step guidance for developing printed circuit boards (PCBs) using Agilex 7 FPGA devices.
FPGA Interface Design
Interactive step-by-step guidance of FPGA Resources and Documentation for Interface Protocols.
FPGA Application Design
The interactive FPGA Application Design Guided Journey provides detailed information on steps to develop applications for FPGA designs.
Software Development
The Software Development Guided Journey is organized into industry-standard stages to help complete your FPGA design.
AI Design
The interactive FPGA AI Design Guided Journey provides step-by-step guidance for developing AI Intellectual Property (IP) Designs.
oneAPI FPGA Development
This interactive journey provides step-by-step guidance to develop an oneAPI DPC++/C++ design for Altera FPGA devices.
Solutions
Use Agilex 7 to accelerate high-throughput compute, analytics, storage, and AI data movement close to processors and memory. PCIe 5.0, CXL, 116 Gbps transceivers, and M-Series HBM2e options help move and process large datasets with adaptable hardware acceleration.
Build high-bandwidth fronthaul, backhaul, optical transport, packet-processing, and security data paths with transceivers up to 116 Gbps. Reprogrammable logic and hardened connectivity help equipment vendors adapt to changing protocols, line rates, and network architectures.
Process and transport high-resolution media with parallel DSP, high-speed serial connectivity, and adaptable interface logic. Agilex 7 supports demanding video-over-IP, format-conversion, image-processing, and evolving broadcast workflows that require high bandwidth and low latency.
Use Agilex 7 for radar, electronic warfare, secure communications, test instrumentation, and other compute- and data-intensive systems. High-performance DSP, wide memory bandwidth, security capabilities, and reconfigurable I/O support long product lifecycles and evolving mission requirements.
Demo Videos
Agilex 7 4K Video IP and Reference Design in Action
Bridging HDMI to DisplayPort while processing live 4K video can be complex. Watch Agilex 7 do it in this demo, then see how Altera video IP and a complete reference design help you build on a working starting point.
DDR5-6400 Performance Demo
Agilex 7 M-Series FPGAs now support DDR5-6400, delivering 14%+ higher DDR5 performance.
Runtime Reconfiguration You Can Trust
Agilex 7 FPGAs deliver reliable dynamic reconfiguration capabilities that allow systems to adapt in real time without disrupting operation, making them ideal for high-performance and evolving infrastructure designs.
Accelerating 200G Connectivity for Modern Networks
This video showcases how Agilex 7 FPGAs enable efficient, high-performance 200G connectivity, delivering the speed, scalability, and power efficiency needed for today’s networking and data center applications.
Demonstration of Interop with 400G DR4 Linear Pluggable Optics
For this interop demo video, Altera implemented a 4x 100G design transmitting 400GbE traffic with 100G-DR4 LPO modules.
Resources
Documentation, downloads, videos, training, and support for Agilex 7.
Common Questions
Use F-Series for balanced workloads, I-Series for demanding processor/I/O links, and M-Series when supported memory hierarchy is central.
Check the exact device and tile configuration in current product documentation. Family-wide feature lists do not guarantee every part includes both.
PCIe provides transport and device transactions. Supported CXL modes add coherency semantics and require compatible host hardware and software.
Compare workload throughput, memory traffic, I/O, tool/IP support and power. Migration requires reimplementation and system validation.
Measure each data-path stage, host transfers and memory efficiency to locate the bottleneck. Peak lane rate does not equal payload throughput.
Suitable devices provide high-speed transceivers and Ethernet resources. Verify tile, hard-IP, buffering and system throughput requirements together.