Agilex 7 FPGA AI Design Guided Journey

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Please select the desired Getting Started with FPGA AI Suite sub-step from the flowchart to the left to view the applicable assets:

FPGA AI Suite Handbook
What is FPGA AI Suite?
Design Considerations Before Beginning
Installing FPGA AI Suite
FPGA AI Suite Tutorial & Design Example Demonstration Applications

Please select the desired Creating Your FPGA AI Suite IP sub-step from the flowchart to the left to view the applicable assets:

Creating an Architecture File for FPGA AI Suite IP
Compiling Your Model with the FPGA AI Suite Compiler
Generating the FPGA AI Suite IP for Integration into an FPGA Design
Optimizing Your FPGA AI Suite IP

Please select the desired Integrating and Deploying Your FPGA AI Suite IP sub-step from the flowchart to the left to view the applicable assets:

Integrating FPGA AI Suite IP into an FPGA Design
Simulation of FPGA AI Suite IP
FPGA Platforms for Your FPGA AI Suite IP Deployment
Software Application Development for use with FPGA AI Suite
Continuing Your FPGA Platform Development

FPGA AI Suite Handbook

picture_as_pdfFPGA AI Suite Handbook

What is the FPGA AI Suite?

picture_as_pdfWhat is the FPGA AI Suite?

FPGA AI Suite Components

picture_as_pdfFPGA AI Suite Components

The FPGA AI Suite Tool Flow

picture_as_pdfThe FPGA AI Suite Tool Flow

The FPGA AI Suite User Flow

picture_as_pdfThe FPGA AI Suite User Flow

The FPGA AI Suite IP

picture_as_pdfThe FPGA AI Suite Sequential IP

picture_as_pdfThe FPGA AI Suite Spatial IP (Beta)

picture_as_pdfThe FPGA AI Suite IP Sequential Architecture

picture_as_pdfHow Does the FPGA AI Suite Sequential IP Overlay Architecture Work?

picture_as_pdfParallelism in the FPGA AI Suite Sequential IP

picture_as_pdfFPGA AI Suite Sequential IP Datapath Component Organization

picture_as_pdfModels Supported by the FPGA AI Suite Sequential IP

picture_as_pdfFPGA AI Suite Sequential IP Model Performance

picture_as_pdfDDR-Free Streaming Performance

The FPGA AI Suite Compiler

picture_as_pdfThe FPGA AI Suite Compiler

The FPGA AI Suite Design Examples

picture_as_pdfThe FPGA AI Suite Design Examples

picture_as_pdfHostless JTAG Design Example

Design Example Components

picture_as_pdfFPGA AI Suite Design Example Utility

picture_as_pdfExample Architecture Bitstream Files

Design Example Software Components

picture_as_pdfOpenVINO™ FPGA Runtime Overview

picture_as_pdfOpenVINO™ FPGA Runtime Plugin

picture_as_pdfFPGA AI Suite Runtime

picture_as_pdfFPGA AI Suite Custom Platform

picture_as_pdfMemory-Mapped Device (MMD) Driver

picture_as_pdfFPGA AI Suite Runtime MMD API

picture_as_pdfBoard Support Package (BSP) Overview

picture_as_pdfAdditional FPGA AI Suite SoC Design Example Software Components

Make These Decisions Early

picture_as_pdfConsider an FPGA AI Suite Design Example as Starting Point

picture_as_pdfDetermine Your Performance Bottlenecks

picture_as_pdfSelect Your FPGA Device

Installing FPGA AI Suite

picture_as_pdfInstalling FPGA AI Suite

Install in a Containerized Environment

picture_as_pdfUsing the FPGA AI Suite Docker Image

Install Locally

picture_as_pdfInstalling the FPGA AI Suite Compiler and IP Generation Tools

picture_as_pdfInstalling the FPGA AI Suite from a Python Package File

Install Packages for the Design Examples

picture_as_pdfInstalling FPGA AI Suite Design Example Prerequisites

Installing FPGA AI Suite Simulation Tools

picture_as_pdfInstalling FPGA AI Suite Simulation Prerequisites

Quick Start Tutorial

picture_as_pdfFPGA AI Suite Quick Start Tutorial

Demonstration Applications

picture_as_pdfPerforming Inference with the FPGA AI Suite Sequential IP without an FPGA Board

FPGA AI Suite Architecture Files

picture_as_pdfPredefined FPGA AI Suite Sequential IP Architecture Files

picture_as_pdfFPGA AI Suite Sequential IP Architecture File Breakdown

picture_as_pdfFPGA AI Suite IP Parameterization

picture_as_pdfCreating an Architecture Files for the FPGA AI Suite Spatial IP

Convert Your Model with OpenVINO™

picture_as_pdfConvert Your Model with OpenVINO™

FPGA AI Suite Model Compilation

picture_as_pdfCompiling a Model

FPGA AI Suite Model Measurement Tools

picture_as_pdfEstimating Model Performance

picture_as_pdfEstimating the Area and Power of an Architecture

picture_as_pdfThe FPGA AI Suite Compiler Report

FPGA AI Suite Compiler Settings

picture_as_pdfFPGA AI Suite Compiler Command Line Options

picture_as_pdfCompiler Inputs and Outputs

FPGA AI Suite IP Generation Utility

picture_as_pdfIP Generation Utility Execution Flows

picture_as_pdfIP Generation Utility Inputs

picture_as_pdfIP Generation Utility Outputs

picture_as_pdfIP Generation Utility Command Line Options

Optimizing Your FPGA AI Suite IP

picture_as_pdfOptimizing Your FPGA AI Suite Sequential IP

Tools for Optimizing Your FPGA AI Suite IP

picture_as_pdfFolding Input

picture_as_pdfParallelizing Inference

picture_as_pdfTransforming the Layout of Input Data

picture_as_pdfFolding Input Layout Transform

picture_as_pdfOutput Tensor In-Memory Format

picture_as_pdfLightweight Layout Transform

picture_as_pdfParallelizing Inference Using FPGA AI Suite with Multiple Lanes and Multiple Instances

Make Precision vs. Performance Trade-offs for Your FPGA AI Suite IP

picture_as_pdfBlock Floating Point (BFP)

picture_as_pdfImproving Layer Accuracy by using Mixed Precision

picture_as_pdfUsing the Mixed Precision Feature

Hyperparameters, Layer Support, and Parameterization

picture_as_pdfFPGA AI Suite IP Supported Layers and Hyperparameter Ranges

picture_as_pdfFPGA AI Suite IP Parameterization

Generate an Optimized FPGA AI Suite Architecture File

picture_as_pdfPerformance Impact of Mixed Precision

picture_as_pdfGenerating an Architecture for Highest Performance

picture_as_pdfGenerating an Architecture Optimized for a Frame Rate Target Value

Directory Structure

picture_as_pdfFPGA AI Suite IP Directory Structure

FPGA AI Suite IP Interface

picture_as_pdfFPGA AI Suite Sequential IP Interface

picture_as_pdfClock and Reset

picture_as_pdfAXI Interface

picture_as_pdfAXI Feature Streaming Interface

picture_as_pdfCSR Map and Descriptor Queue

picture_as_pdfInterfacing the FPGA AI Suite Sequential IP to Avalon® Memory Map (AVMM)

Using FPGA AI Suite IP in Platform Designer

picture_as_pdfInstantiating the FPGA AI Suite Sequential IP in Platform Designer

picture_as_pdfResource Utilization of FPGA AI Suite Sequential IP

Simulating Your FPGA AI Suite IP

picture_as_pdfThe FPGA AI Suite simulation command (dla_sim.py)

picture_as_pdfSimulating an FPGA AI Suite IP

picture_as_pdfExamples of Simulating an FPGA AI Suite IP

Using FPGA AI Suite as a PCIe -Attach Platform

picture_as_pdfUsing FPGA AI Suite as a PCIe -Attach Platform

picture_as_pdfPCIe -Attach System Overview

picture_as_pdfPCIe -Attach Design Example Hardware

picture_as_pdfOFS PCIe -Attach Design Example Components

picture_as_pdfOFS PCIe -Attach Hardware Components

picture_as_pdfOFS PCIe -Attach Software Components

Using FPGA AI Suite in Hostless On-Chip Parameter Mode

picture_as_pdfUsing FPGA AI Suite in Hostless On-Chip Parameter Mode

picture_as_pdfGenerating Artifacts for On-Chip-Parameter Operation

picture_as_pdfHostless DDR-Free Design Example System Overview

picture_as_pdfHostless DDR-Free Design Example Hardware

picture_as_pdfHostless DDR-Free Design Example Quartus Prime System Console

picture_as_pdfHostless DDR-Free Design Example JTAG to Avalon MM Host Register Map

picture_as_pdfChanging the ML Model in a On-Chip Parameter Architecture

Using the FPGA AI Suite Sequential IP Hostless On-Chip Parameter DDR-Free Mode

picture_as_pdfUsing the FPGA AI Suite Sequential IP Hostless On-Chip Parameter DDR-Free Mode

picture_as_pdfHostless JTAG Hardware Components

picture_as_pdfHostless JTAG Software Components

Using FPGA AI Suite as an Embedded Platform

picture_as_pdfUsing FPGA AI Suite as an Embedded Platform

picture_as_pdfFPGA AI Suite SoC Design Example Inference Sequence Overview

picture_as_pdfMemory-to-Memory (M2M) Variant Design

picture_as_pdfStreaming-to-Memory (S2M) Variant Design

picture_as_pdfTop Level

picture_as_pdfThe SoC Design Example Platform Designer System

picture_as_pdfFabric EMIF Design Component

picture_as_pdfPLL Configuration

picture_as_pdfYocto Build and Runtime Linux Environment

picture_as_pdfSoC Design Example MMD Layer Hardware Interaction Library

picture_as_pdfFPGA AI Suite SoC Design Example Run Process

picture_as_pdfFPGA AI Suite SoC Design Example Build Process

Using FPGA AI Suite in Video Applications

picture_as_pdfUsing FPGA AI Suite in Video Applications

picture_as_pdfNios® V Subsystem

picture_as_pdfBuilding the Stream Controller Module

picture_as_pdfBuilding the Streaming Demonstration Applications

picture_as_pdfRunning the Streaming Demonstration

Using the FPGA AI Suite IP with High Bandwidth Memory on Stratix® 10 MX and Agilex™ 7 M-Series Devices

picture_as_pdfUsing the FPGA AI Suite IP with High Bandwidth Memory on Stratix® 10 MX and Agilex™ 7 M-Series Devices

picture_as_pdfCurrent FPGA AI Suite IP Implementation With DDR

picture_as_pdfHBM Connection Considerations

picture_as_pdfMemory Size and Bandwidth Considerations

picture_as_pdfMemory Data Width Considerations

Developing Software Applications with the FPGA AI Suite

picture_as_pdfDeveloping Software Applications with the FPGA AI Suite

picture_as_pdfUnderstanding the FPGA AI Suite Runtime Software Stack

picture_as_pdfUsing the FPGA AI Suite Sequential IP Software Emulation

picture_as_pdfRunning Inference on the FPGA AI Suite IP Without the OpenVINO™ Runtime

picture_as_pdfFiles Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility

picture_as_pdfBuilding the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility

picture_as_pdfRunning the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility

picture_as_pdfFPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application

Interface Protocols

infoAgilex™ 7 FPGA Interface Protocol Design

Application Design

infoAgilex™ 7 FPGA Application Design

System Architecture

infoAgilex™ 7 System Architecture Guided Journey

Agilex® 7 FPGA AI Design Guided Journey

Please select the desired journey step from the flowchart to view the applicable assets.

Please select the desired Getting Started with FPGA AI Suite sub-step from the flowchart to the left to view the applicable assets:

Please select the desired Creating Your FPGA AI Suite IP sub-step from the flowchart to the left to view the applicable assets:

Please select the desired Integrating and Deploying Your FPGA AI Suite IP sub-step from the flowchart to the left to view the applicable assets: