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Agilex® 7 I-Series
Bandwidth-intensive FPGAs and SoCs with transceivers up to 116 Gbps, PCIe 5.0, and cache- and memory-coherent CXL attach to processors.
Interconnect Innovations
I-Series devices offer the highest-performance I/O interfaces for bandwidth-intensive applications. Manufactured on 10 nm SuperFin process technology, the series builds on F-Series features with transceiver rates up to 116 Gbps, PCIe 5.0 support, and cache- and memory-coherent attach to processors using Compute Express Link (CXL).
Up to
116
Gbps transceiver data rate
Industry’s
1st
PCIe 5.0 x16 PCI-SIG listed, 32 GT/s FPGA
Bandwidth:
4X
Higher CXL bandwidth per port vs. other FPGA Compute Express Link (CXL) implementations
Benefits
Support the Most Demanding Bandwidth Requirements
Support industry-leading data rates up to 116 Gbps across a wide range of applications, with configurable networking support including hardened MAC, PCS, and forward error correction for Ethernet rates up to 400GE.
High-Performance and Scalable with Fast Data Transfer Rates
Optimize I/O functionality and allow multiple hosts to connect through a PCIe 5.0 x16 interface, with data transfer rates from 2.5 GT/s to 32.0 GT/s.
High-Speed, Low-Latency Cache and Memory-Coherent Interface
Compute Express Link provides a high-speed, low-latency cache and memory-coherent interface to CPUs and workload accelerators, for optimal workload acceleration and connection to FPGA-based discrete accelerators.
Specifications
Logic Elements
Fabric innovations allow over 4 million logic elements in a single monolithic fabric.
Heterogeneous 3D SiP Transceivers
Transceivers on heterogeneous 3D system-in-package tiles support bandwidth capacities ranging up to 32 Gbps NRZ and up to 116 Gbps PAM4.
High-Performance Crypto Blocks
Hardened 200G half-duplex crypto cores support AES-GCM encryption and decryption, with MACsec IP to secure network traffic.
Quad-Core Arm Cortex-A53 SoC
Selected devices integrate a hardened quad-core Arm Cortex-A53 processor option for control-plane software and tightly coupled hardware acceleration.
PCIe 5.0 and Compute Express Link
R-Tile provides PCIe 5.0 x16 connectivity at up to 32 GT/s and CXL attach for cache- and memory-coherent host connection, with higher CXL bandwidth per port than other FPGA implementations.
Second-Generation Hyperflex™ FPGA Architecture
Hyper-Registers distributed throughout the fabric enable significant design optimization, delivering higher performance, lower total power, greater design functionality, and increased designer productivity.
Secure Device Manager
A dedicated Secure Device Manager controls configuration, authentication, bitstream encryption, key protection, and tamper monitoring across Agilex 7 devices.
Product Package & Combination Selector
Start Design
Start an Agilex 7 I-Series design with transceiver and PCIe development kits, production design software, validated IP, example designs, and guided design journeys for architecture, board, interface, application, AI, and software development.
Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile)
Evaluate and prototype high-speed serial transceiver designs across QSFPDD800, OSFP, and PCIe 4.0, with soldered-down and DIMM-based DDR4 memory for data-intensive workloads.
Agilex 7 FPGA I-Series Development Kit (2x R-Tile and 1x F-Tile, Rev B)
Prototype PCIe 5.0, CXL, and high-speed networking designs with dual QSFPDD ports for up to 400 Gbps aggregate throughput, PCIe 5.0 and CXL x16 via edge connectors and MCIO, and onboard DDR4.
Agilex 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile)
Evaluate high-speed transceiver interfaces together with SoC integration for designs that pair the hardened processor system with bandwidth-intensive data paths.
Partner Boards
Find production and evaluation boards for Agilex 7 I-Series devices from Altera partners when a reference kit does not match the target form factor.
Video and Vision Processing Suite
A collection of next-generation Altera IP functions that speed development of custom video and image processing designs.
Nios V Processors
Next-generation soft processor IP that brings the open-source RISC-V architecture to FPGA designs.
PCI Express FPGA IP
Implement PCIe 5.0 endpoints and root ports with hardened R-Tile connectivity for host attach and workload offload.
Compute Express Link (CXL) FPGA IP
Build coherent, low-latency attach to host processors for workload acceleration and memory expansion.
Ethernet FPGA IP
Implement configurable networking with hardened MAC, PCS, and FEC for Ethernet rates up to 400GE.
Quartus Prime Pro Edition Design Software
Compile, place and route, verify timing, and program Agilex 7 I-Series FPGA and SoC designs.
FPGA AI Suite
Build and deploy AI inference pipelines that use Agilex 7 variable-precision DSP and programmable logic resources.
P4 Suite for FPGAs
Describe and compile packet-processing pipelines in P4 for high-throughput networking designs.
Solutions
Attach accelerators coherently to host processors over PCIe 5.0 and CXL, and keep inference pipelines fed with 116 Gbps interfaces and adaptable data paths
Accelerate packet processing, traffic management, optical transport, and secure network functions with hardened MAC, PCS, and FEC for Ethernet rates up to 400GE.
Build fronthaul, backhaul, beamforming, and radio-access processing with deterministic DSP, 116 Gbps transceivers, and interfaces that evolve with network standards.
Offload compute, storage, security, and data-movement workloads with PCIe 5.0 x16 host attach, CXL coherency, and adaptable acceleration.
Integrate real-time control, machine vision, robotics, and networking on a reprogrammable platform with deterministic processing and optional Arm-based SoC control.
Process high-resolution imaging and sensor data in real time with parallel processing, high-speed I/O, and long product lifecycles suited to regulated equipment.
Support radar, electronic warfare, secure communications, and mission systems with high-throughput data paths, hardened crypto, and adaptable interfaces.
Capture, move, and analyze wide, fast data streams using 116 Gbps transceivers, PCIe 5.0 host attach, and reconfigurable acquisition paths.
Process and transport high-resolution media with high-speed serial I/O, video and vision IP, and adaptable format and protocol support.
Accelerate cryptography and secure data movement with hardened 200G AES-GCM crypto cores and MACsec IP for protected network traffic.
Resources
Documentation
Training and Learning
Common Questions
Choose I-Series when supported PCIe 5.0, CXL or higher-rate I/O is required. Compare specific tile and device options.
Use a compatible FPGA implementation, host platform, firmware and software stack supporting the intended CXL mode.
Account for transaction overhead, transfer sizes, host memory behavior and DMA efficiency. Measure payload throughput under the real workload.
Check host capability, lane wiring, reference clocks, signal integrity and IP configuration. Inspect link-training status before changing application logic.
Use it when the required interface and channel budget justify that rate. Confirm package/tile availability and the supported protocol implementation.
Supported CXL attachment can enable coherent memory sharing. Actual benefit depends on workload access patterns and compatible host infrastructure.
Ready to Order
Confirm the device, transceiver tile mix, package, speed grade, temperature range, and lifecycle requirements in the current I-Series product table. Then contact an authorized distributor or an Altera representative for availability and purchasing support.