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Agilex® 7 M-Series
Compute- and memory-intensive FPGAs and SoCs with in-package HBM2E, DDR5, a hardened memory NoC, and transceivers up to 116 Gbps.
Built for the Highest Memory Bandwidth
M-Series devices are optimized for compute- and memory-intensive applications. Built on Intel 7 process technology, they extend I-Series features with an extensive memory hierarchy, including in-package HBM2E, high-efficiency DDR5 interfaces, and a hardened memory Network-on-Chip that maximizes usable bandwidth.
Up to
1
RBps the Industry’s highest memory bandwidth FPGA
Industry’s highest
DSP
compute density in an HBM-enabled FPGA
Industry’s
1st
DDR5-enabled high-end FPGA
Benefits
Hardened Memory Network-on-Chip
A hardened memory NoC unlocks the industry’s highest memory bandwidth, up to 1 TBps, using in-package HBM2E with up to 32 GB capacity and hardened DDR5 and LPDDR5 memory controllers supporting 5,600 Mbps.
In-Package HBM2E Memory
Integrated high-bandwidth memory places large, fast memory in the same package as the fabric, supporting bandwidth-bound workloads without the board area and power cost of equivalent external memory.
Variable-Precision DSP
Configurable DSP blocks deliver up to 38 TFLOPS of FP16 performance for AI, signal processing, and other compute-intensive workloads, alongside up to 3.9 million logic elements.
M Series specification
FPGA Fabric
Second-generation Hyperflex® core fabric — the densest, highest-frequency programmable logic Altera builds.
Headline Specifications
- Up to 3.9M logic elements
- Up to 1.3M ALMs / 5.2M registers
- Up to 12,300 DSP blocks
- 370 Mb embedded memory
- Up to 37 TFLOPS FP16
- Intel 7 process
Full Specifications
Full Specifications
- Logic elements
- 3,245,000 (AGM 032) / 3,851,520 (AGM 039)
- ALMs
- 1,100,000 / 1,305,600
- ALM registers
- 4,400,000 / 5,222,400
- M20K blocks
- 15,932 (311 Mb) / 18,960 (370 Mb)
- DSP blocks
- 9,375 / 12,300
- 18×19 multipliers
- 18,750 / 24,600
- TFLOPS (FP32 / FP16)
- 14 / 28 · 18.4 / 37
- Fabric PLL / I/O PLL
- 8 / 16
- Architecture
- 2nd-generation Hyperflex, Hyper-Registers on every routing segment and at all functional block inputs
- Process
- Intel 7
- Product lines
- AGM 032, AGM 039
Hard Memory Network-on-Chip
A hardened, high-bandwidth interconnect that moves data between the fabric and every attached memory — without consuming fabric routing or logic.
Headline Specifications
- Over 1 TBps aggregate memory bandwidth
- Two independent hardened NoCs
- Up to 12,300 DSP blocks
- Zero fabric resources consumed
- AXI4 / AXI4-Lite interface
- Full any-to-any crossbar
Full Specifications
Full Specifications
- Aggregate memory bandwidth
- Over 1 TBps
- Per-subsystem contents
- PLL, subsystem manager (SSM), and multiple NoC segments
- Building blocks
- Initiator (INIU), Target (TNIU), Switch
- Interconnect links
- 512-bit high-speed links between switches
- Protocol
- AXI4 (mainband) and AXI4-Lite (sideband) with QoS, bandwidth limiter, transaction limiter
- Crossbar behaviour
- Every initiator can reach every target on the same NoC side
- HBM2E targets
- 16 AXI targets per HBM2E stack (one per pseudo-channel)
- Fabric NoC option
- AXI read-response data routed into the fabric via M20K columns
- Attached memories
- HBM2E (via UIB), DDR4 / DDR5 / LPDDR5 (via GPIO-B I/O banks), HPS
SDM — Secure Device Manager
A dedicated, triple-redundant security processor that owns configuration, boot, and every security feature in the device.
Headline Specifications
- Triple-redundant security processor
- AES-256 bitstream encryption
- ECDSA-256/384 authentication
- PUF-based key storage
- Side-channel mitigation
- Enables FIPS 140-3 Level 2
Full Specifications
Full Specifications
- Architecture
- Triple-redundant processor; single point of entry for all JTAG and configuration commands
- Certification
- Enables system certification to FIPS 140-3 Level 2
- Crypto engines
- AES-256, SHA-256/384, ECDSA-256/384 accelerators; multi-factor authentication
- Bitstream security
- Authenticated FPGA configuration, bitstream encryption, secure key provisioning
- PUF
- Physically unclonable function key storage
- HPS boot
- SDM bootstraps the HPS so it boots with the same security features as the FPGA
- Attestation
- Platform attestation via the SPDM protocol
- Anti-tamper
- Runtime sensors, active tamper detection and response, physical anti-tamper
- Attached memories
- HBM2E (via UIB), DDR4 / DDR5 / LPDDR5 (via GPIO-B I/O banks), HPS
- Manufacturing
- Black key provisioning; secure RMA
- Runtime
- User-mode access to hardened cryptographic engines as a service
- Configuration model
- Sector-based; local sector managers configured in parallel; partial reconfiguration, remote system update, sector or full-device zeroization
- Configuration schemes
- AS (664 Mbps), Avalon-ST ×32 (4 Gbps) / ×16 / ×8, JTAG (30 Mbps), CvP over PCIe 1.0–5.0
HPS — Hard Processor System
A hardened quad-core Arm Cortex-A53 application processor with its own memory controller and peripherals, booted securely by the SDM.
Headline Specifications
- Quad-core Arm Cortex-A53
- Up to 1.5 GHz
- 1 MB shared L2 cache
- 13,800 MIPS at 1.5 GHz
- Hard DDR4 memory controller
Full Specifications
Full Specifications
- Cores
- Quad-core Arm Cortex-A53 MPCore, Armv8-A
- Frequency
- Up to 1.5 GHz
- Performance
- 2.3 MIPS/MHz — 13,800 MIPS at 1.5 GHz
- L1 cache
- 32 KB I-cache (parity) + 32 KB D-cache (ECC) per core
- L2 cache
- 1 MB shared, 8-way set associative, TAG RAM parity and data RAM ECC
- On-chip RAM
- 256 KB
- FPU / SIMD
- Arm NEON media engine; single- and double-precision FPU
- Virtualization
- System memory management unit (SMMU); cache coherency unit
- Memory controller
- Hard DDR4 up to 3,200 Mbps, 40-bit (32+8 ECC); 72-bit (64+8 ECC) in some packages
- Peripherals
- 3× 1G EMAC, 2× USB 2.0 OTG, 5× I²C, 2× UART, 4× SPI, NAND flash controller, SD/SDIO/MMC (eMMC 5.0), 8-channel DMA
- I/O
- 48 HPS direct I/Os; up to 2 FPGA I/O banks assignable to the HPS
- Fabric bridges
- HPS-to-FPGA (32/64/128-bit AXI), lightweight HPS-to-FPGA (32-bit AXI), FPGA-to-HPS (128/256/512-bit ACE-Lite)
- Debug
- Arm CoreSight
DDR5 Interface
Fourth-generation hardened DDR5 memory controller and PHY — the industry's first DDR5-enabled high-end FPGA.
External Memory
- 6,400 Mbps DDR5
- Hardened memory controller
- 40-bit component / 2×40 DIMM
- Industry's first DDR5-enabled high-end FPGA
DDR5 Interface
DDR5 Interface
- Controller
- Hardened (fourth-generation scalable integrated controller and PHY)
- Maximum data rate
- 6,400 Mbps
- Maximum width
- 40-bit component / 2×40 DIMM
- EMIF clocking
- 3,200 MHz external memory interface clocking
- Max EMIF ×72 instances
- 4 (AGM 032)
- Fabric access path
- Via the hard memory NoC (GPIO-B I/O bank subsystems)
- Fabric resources
- None consumed — controller and PHY are hardened
LPDDR5 Interface
Hardened LPDDR5 controller and PHY for power-efficient, high-bandwidth memory at the edge of the package.
External Memory
- 6,400 Mbps LPDDR5
- Hardened memory controller
- 4×16 maximum width
- Fed by the hard memory NoC
LPDDR5 Interface
LPDDR5 Interface
- Controller
- Hardened (fourth-generation scalable integrated controller and PHY)
- Maximum data rate
- 6,400 Mbps
- Maximum width
- 4×16
- EMIF clocking
- 3,200 MHz external memory interface clocking
- Fabric access path
- Via the hard memory NoC (GPIO-B I/O bank subsystems)
- Fabric resources
- None consumed — controller and PHY are hardened
DDR4 Interface
Hardened DDR4 controller and PHY, including DIMM support, for mainstream and legacy memory attach.
External Memory
- 3,200 Mbps DDR4
- Hardened memory controller
- 40-bit component / 72-bit DIMM
- QDR IV supported via soft controller
DDR4 Interface
DDR4 Interface
- Controller
- Hardened (fourth-generation scalable integrated controller and PHY)
- Maximum data rate
- 3,200 Mbps
- Maximum width
- 40-bit component / 72-bit DIMM
- QDR IV (soft controller)
- 2,133 Mbps, 36-bit
- EMIF clocking
- 3,200 MHz external memory interface clocking
- Fabric access path
- Via the hard memory NoC (GPIO-B I/O bank subsystems)
- HPS memory controller
- DDR4 up to 3,200 Mbps, 40-bit (32+8 ECC); 72-bit in some packages
HBM2e
Two HBM2E DRAM stacks integrated in-package beside the fabric, delivering roughly ten times the bandwidth of DDR5.
In-Package Memory
- Up to 32 GB in-package HBM2e
- 820 GBps total bandwidth
- 410 GBps per stack
- Two stacks per device
- 16 pseudo-channels per stack
HBM2e
HBM2e
- Stacks per device
- 2 (maximum of two HBM2E interfaces)
- Capacity per stack
- 8 GB (4H) or 16 GB (8H)
- Total capacity
- 16 GB or 32 GB — non-HBM options also available
- Bandwidth per stack
- 410 GBps
- Total aggregate bandwidth
- 820 GBps
- Channels
- 8 independent 128-bit channels per stack
- Pseudo-channels
- 16 independent 64-bit pseudo-channels per stack
- Transfer rate
- Up to 3.2 Gbps/pin at the fastest speed grade
- Die density
- 2 GB per DRAM die
- ECC
- 8 extra bits per pseudo-channel; SECDED
- Attach
- EMIB bridge to the Universal Interface Block Subsystem (UIBSS) containing HBM controller, PHY, and I/O
- Fabric access
- Exclusively via the hard memory NoC — direct fabric-to-HBM2E access is not supported
- Voltage
- 1.2 V I/O and 1.2 V DRAM core
- Packages
- 4700B (32 GB) and 4700A (16 / 32 GB)
PCIe 5.0
Hardened PCIe 5.0 ×16 endpoint and root port in a dedicated R-Tile chiplet, ready for direct attach to industry-standard server CPUs.
Host Interface · R-Tile
- PCIe 5.0 ×16 endpoint and root port
- 32 GT/s per lane
- Up to two R-Tiles — 32 PCIe lanes
- Bifurcation: 2×8 EP or 4×4 RP
- SR-IOV: 8 PFs / 2K VFs
PCIe 5.0
PCIe 5.0
- Maximum generation and width
- PCIe 5.0 ×16, endpoint and root port
- Per-lane rate
- 32 Gbps NRZ (32 GT/s)
- R-Tiles per device
- Up to 2 (package 3184G); 1 in packages 4700A and 4700D
- Maximum PCIe lanes
- 32
- PCIe / CXL controllers
- 2 per R-Tile
- Bifurcation
- 2×8 endpoint or 4×4 root port
- Virtualization
- SR-IOV — 8 physical functions / 2K virtual functions; VirtIO; Scalable IOV; Shared Virtual Memory
- Other features
- TL bypass, autonomous hard IP, separate header and payload user interfaces, Precise Time Management, PIPE Direct
- Also available
- F-Tile provides PCIe 4.0 ×16 hard IP — up to 4 PCIe controllers in packages 3184B / 4700B / 4700C
- Configuration via Protocol
- CvP over PCIe 1.0–5.0
CXL
Hardened Compute Express Link IP that lets the FPGA attach coherently to a host CPU for cache- and memory-sharing acceleration.
Coherent Attach · R-Tile
- Selected features support CXL 1.1 and 2.0
- Up to PCIe 5.0 ×16 endpoint
- Type 1, Type 2, and Type 3 devices
- Up to 32 CXL lanes
CXL
CXL
- Tile
- R-Tile (hardened CXL IP)
- Link
- Up to PCIe 5.0 ×16 endpoint
- Specification versions
- Selected features support the CXL 1.1 and 2.0 specifications
- Device types
- Type 1, Type 2, or Type 3 — via encrypted soft logic layered on the hardened IP
- Maximum CXL lanes
- 32 (AGM 032 and AGM 039)
- CXL controllers
- 2
- Memory
- Mix and manage different memory types and controllers
- Availability
- Devices with at least one R-Tile (I-Series and M-Series)
116G Transceivers
F-Tile transceivers running at 116 Gbps PAM4 per lane — the fastest transceivers Altera ships.
SerDes · F-Tile
- 116 Gbps PAM4 per channel
- 58 Gbps NRZ and PAM4
- 32 Gbps NRZ (FGT)
- Up to 4 F-Tiles per device
- Up to 64 FGT + 16 FHT channels
116G Transceivers
116G Transceivers
- Transceiver types
- FGT (general purpose) and FHT (high speed) — M-Series has both
- FGT range
- 1–32 Gbps NRZ; 20–58 Gbps PAM4
- FHT ranges
- 24–29 Gbps NRZ and PAM4; 48–58 Gbps NRZ and PAM4; 96–116 Gbps PAM4
- Per-tile capability
- 4× 116 Gbps PAM4, or 12× 58 Gbps PAM4, or 16× 32 Gbps NRZ
- Maximum device channels
- 64 FGT @ 32G NRZ, 48 FGT @ 58G PAM4, 16 FHT @ 58G NRZ, 16 FHT @ 116G PAM4
- Maximum F-Tiles
- 4 (packages 3184B, 4700B, 4700C)
- FEC
- RS and KP FEC on both FGT and FHT
- Hard IP in tile
- Ethernet MAC / PCS / FEC and PCIe 4.0 ×16
- Protocols
- CEI, Ethernet, CPRI, FlexE, 300G Interlaken, Fibre Channel, SerialLite IV, OTN, JESD204B/C, FlexO, IEEE 1588, GPON, SDI, V-by-One, HDMI, DisplayPort
- Modes
- PMA Direct mode; dynamic reconfiguration
400 GbE
Hardened Ethernet MAC, PCS, and FEC in the F-Tile — from 10 GbE up to a single 400 GbE port, with no fabric logic consumed.
Ethernet · F-Tile
- Up to 400 GbE hard MAC, PCS, and FEC
- 10, 25, 40, 50, 100, 200, 400 GbE
- IEEE 1588 PTP
- RS-FEC and KP FEC
- Up to 4 Ethernet hard IP blocks
400 GbE
400 GbE
- Tile
- F-Tile
- Rates
- 10, 25, 40, 50, 100, 200, and 400 GbE hardened MAC, PCS, and FEC
- Per-tile configurations
- 16× 10/25 GbE, or 8× 50 GbE, or 8× 40 GbE, or 4× 100 GbE, or 1× 400 GbE — each with MAC, PCS, and FEC
- Ethernet hard IP blocks per device
- 4
- FEC
- KR/KP RS-FEC; Flex-O FEC; FlexE PCS and FEC; Fibre Channel and CPRI FEC
- Additional features
- Ethernet over OTN mode, SyncE, CR/KR (AN/LT), IEEE 1588 PTP, MAC/PCS/FEC bypass, PMA Direct mode
EMIB
Embedded Multi-die Interconnect Bridge — the silicon bridge that stitches the fabric die to transceiver tiles and HBM2E stacks inside the package.
Advanced Packaging
- 2.5D embedded-bridge interconnect
- In high-volume manufacturing since 2017
- Connects the fabric die to F-Tiles, R-Tiles, and HBM2E
- Small bridge die instead of a full silicon interposer
- Up to 4 AIB interfaces (AGM 032)
EMIB
EMIB
- What it is
- A small bridge die with multiple routing layers, embedded in a cavity in the package substrate
- Role in M-Series
- Silicon bridge between the HBM2E stacks and the UIB subsystem, and between the fabric die and the heterogeneous 3D SiP transceiver tiles
- Advantage vs. interposer
- Uses a very small bridge die rather than a large silicon interposer, so I/O signal and power-integrity characteristics are unaffected
- Bump pitch approach
- Tight microbump pitch is required only at the bridge; the rest of the die-core region retains a loose pitch
- Maturity
- High-volume manufacturing since 2017, with assembly yields comparable to standard FCBGA of equal complexity
- Stated benefits
- Enables large heterogeneous die complexes; supports high-data-rate die-to-die signalling with simple driver and receiver circuitry; each link can be individually optimized
- Maximum AIB interfaces
- 4 (AGM 032)
- Package migration
- Multiple devices share identical package footprints, allowing migration across densities
Product Package & Combination Selector
Start Design
Start an Agilex 7 M-Series design with the HBM2e development kit, production design software, memory and interface IP, example designs, and guided design journeys for architecture, board, interface, application, AI, and software development.
Agilex 7 FPGA M-Series Development Kit — HBM2e Edition (3x F-Tile and 1x R-Tile)
Prototype memory- and bandwidth-intensive designs on a platform that pairs in-package HBM2e with DDR5 DIMM, DDR5 component, and LPDDR5 interfaces, PCIe 5.0 x16 via MCIO, two QSFPDD ports, and one QSFPDD800 port.
Agilex 7 M-Series Partner Boards
Find production and evaluation boards for Agilex 7 M-Series devices from Altera partners when the reference kit does not match the target form factor.
HBM2e Memory Interface FPGA IP
Implement high-bandwidth, low-latency, low-power memory access to in-package HBM2E on M-Series devices.
DDR5, DDR4, LPDDR5, and LPDDR4 External Memory Interfaces FPGA IP
Connect external memory with hardened controllers for faster data processing and more efficient power use across networking, cloud, and edge designs.
Compute Express Link (CXL) FPGA IP
Build coherent, high-bandwidth attach to compatible server processors for workload offload and memory expansion.
Example Designs
Find example designs, documentation, and software tools that shorten bring-up and reduce time to production.
Quartus Prime Pro Edition Design Software
Compile, place and route, verify timing, and program Agilex 7 M-Series FPGA and SoC designs.
FPGA AI Suite
Build and deploy AI inference pipelines that use M-Series variable-precision DSP, HBM2E bandwidth, and programmable logic.
Altera FPGA Add-on for oneAPI Base Toolkit
Develop high-level FPGA accelerators with the oneAPI programming model and optimization flow.
Ashling RISCFree IDE
Develop and debug software for Nios V and hardened processor systems in E-Series SoC designs.
Solutions
Feed large models and data sets from in-package HBM2E into variable-precision DSP with up to 38 TFLOPS of FP16 performance, keeping inference and training pipelines fed without external memory bottlenecks.
Offload compute, storage, security, and data-movement workloads with PCIe 5.0, CXL coherent attach, and up to 1 TBps of memory bandwidth for infrastructure that keeps changing.
Build fronthaul, backhaul, beamforming, and radio-access processing with deterministic DSP, transceivers up to 116 Gbps, and memory bandwidth that scales with channel count.
Integrate real-time control, machine vision, robotics, and networking on a reprogrammable platform with deterministic processing and a wide memory hierarchy.
Process high-resolution imaging and sensor data in real time with parallel DSP, large on-package memory, and long product lifecycles that suit regulated equipment.
Support sensor fusion, in-vehicle networking, and software-defined vehicle platforms with adaptable interfaces and high-throughput data paths.
Support radar, electronic warfare, secure communications, and mission systems with high-throughput DSP, robust security, and adaptable interfaces for long deployment cycles.
Capture, buffer, and analyze wide, fast data streams using HBM2E capacity, 116 Gbps transceivers, and reconfigurable acquisition paths.
Process and transport high-resolution media with parallel DSP, high-speed serial I/O, and adaptable format and protocol support for production and contribution workflows.
Accelerate cryptography, deep packet inspection, and secure data movement with hardened configuration security and programmable data paths.
Resources
Training and Learning
Support and Community
Common Questions
Use F-Series for balanced workloads, I-Series for demanding processor/I/O links, and M-Series when supported memory hierarchy is central.
Check the exact device and tile configuration in current product documentation. Family-wide feature lists do not guarantee every part includes both.
PCIe provides transport and device transactions. Supported CXL modes add coherency semantics and require compatible host hardware and software.
Compare workload throughput, memory traffic, I/O, tool/IP support and power. Migration requires reimplementation and system validation.
Measure each data-path stage, host transfers and memory efficiency to locate the bottleneck. Peak lane rate does not equal payload throughput.
Suitable devices provide high-speed transceivers and Ethernet resources. Verify tile, hard-IP, buffering and system throughput requirements together.
Ready to Order
Confirm the device, HBM capacity, package, speed grade, transceiver tile, temperature range, and lifecycle requirements in the current M-Series product table. Then contact an authorized distributor or an Altera representative for availability and purchasing support.
Supporting link View the M-Series product table