Arria® 10 GT FPGA
Enabled with up to 78 full-duplex transceivers with data rates up to 25.78 Gbps chip-to-chip.
Explore the Arria® 10 GT FPGA
At 20nm, Arria 10 GX FPGAs deliver high performance, supporting data rates up to 17.4 Gbps chip-to-chip, 12.5 Gbps backplane, and up to 1,150K equivalent LEs.
Key Features
| 25.78 Gbps Transceiver Speed | Support communication transfer speeds of up to 25.78 Gbps between various chips or components within an electronic system. |
| Enhanced Floating-Point Capabilities | DSP blocks with integrated floating-point capabilities provide high-performance computing and can deliver up to 1.5 TeraFLOPs of processing power. |
| Increased External Memory Bandwidth | This device offers seven 32-bit DDR4 memory interfaces operating at up to 2,400 Mbps, delivering increased external memory bandwidth, simplifying design, and optimizing memory controller usage. |
Benefits
High-Speed Transceivers and DSP Processing
Enables high-speed connectivity with integrated transceivers supporting advanced serial protocols, allowing for reliable data transfer in applications such as optical networking, wireless infrastructure, and data communications.
Flexible Embedded Processing Options
Provides robust signal integrity and low-latency performance to simplify the design of complex high-bandwidth systems that require consistent throughput and reliable link operation.
Power-Efficient Performance for Complex Designs
Supports advanced clocking and jitter management features, allowing designers to meet demanding interface timing requirements across a variety of high-speed interconnect standards.
Product Package & Combination Selector
Start Design
Start your Arria 10 GT FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
Interlaken IP
The Interlaken FPGA IP core is Interlaken Protocol Definition v1.2 compliant and allows system developers to achieve high-bandwidth throughput in their systems.
O-RAN FPGA IP
The IP manages transmission and receiver windows, which you can place relative to the air interface based on predefined or measured transport delay.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Quartus® Prime Pro Edition Design Software
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus® Prime Standard Edition Design Software
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Solutions
Arria® 10 GT FPGAs for Wireline
Arria® 10 GT FPGAs for Broadcast and Pro AV
Arria® 10 GT FPGAs for Test & Measurement
Resources
Documentation, downloads, videos, training, and support for Cyclone V ST FPGA
Common Questions
Choose GT when supported serial rates above GX capability are required. Compare channel count, logic and package requirements separately.
Check the device datasheet for the chosen speed grade, channel type and operating conditions before setting the transceiver configuration.
Line rate includes encoding and protocol overhead. Useful payload rate also depends on packet sizes and higher-level traffic behavior.
Check channel loss, clocks, power integrity, equalization and supported backplane rates. Validate with controlled patterns and error measurements.
Use it when required accuracy and dynamic range justify floating point. Verify available DSP resources and sustained data-path throughput.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.