Arria® 10 SX
Power-efficient, mid-range SoC FPGAs integrating a dual-core Arm Cortex-A9 processor with high-performance FPGA fabric.
Explore the Arria® 10 SX SoC FPGA
At 20 nm, Arria 10 SX SoC FPGAs feature a dual-core Arm Cortex*-A9 hard processor system (HPS), support up to 48 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip and 12.5 Gbps backplane communications, while providing up to 660K equivalent logic elements.
Key Features
| Enhanced Arm Processor | Dual-core Arm Cortex-A9 MPCore processor with Arm CoreSight* debug and trace technology. At 1.5 GHz, the processor provides increased performance and reduced power. |
| Improved SoC Architecture | With three Ethernet MAC cores, 256 KB Scratch-RAM, supports 8- and 16-bit NAND flash devices, embedded MultiMediaCard (eMMC) SD/SDIO/MMC cards, and 72-bit DDR3/4 memory for building an improved architecture. |
| Enhanced Security | This SoC FPGA supports secure boot with Elliptical Curve Digital Signature Authentication (EC DSA) authentication, with a layered public key infrastructure for root of trust support, Advanced Encryption Standard (AES), and new anti-tamper features |
Benefits
Integrated Processing and Programmable Logic
Combines FPGA fabric with integrated dual-core Arm Cortex-A9 processors, enabling hardware-software co-design for embedded applications that require both programmable logic and software programmability.
Flexible Embedded System Integration
Simplifies system integration by consolidating processing, I/O, and custom acceleration on a single device, reducing board complexity and improving design efficiency.
Power-Efficient Performance for Complex Designs
Provides flexibility for control-plane, data-plane, and system management functions, supporting a variety of embedded applications such as industrial automation, automotive, and communications systems.
Product Package & Combination Selector
Start Design
Start your Arria 10 SX SoC FPGA design – choose a design phase below to jump to the right tools, guides, and resources.
eCPRI FPGA IP
The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0. It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.
Turbo-V FPGA IP Core
Forward-error correction (FEC) channel codes commonly improve the energy efficiency of wireless communication systems.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Quartus® Prime Pro Edition Design Software
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Standard Edition Design Software
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Solutions
Arria 10 SX SoC FPGAs for Industrial
Arria 10 SX SoC FPGAs for Transportation
Arria 10 SX SoC FPGAs for Medical
Resources
Documentation, downloads, videos, training, and support for Arria 10 SX SoC FPGA.
Common Questions
Use the documented HPS-to-FPGA interfaces and address map. Match bridge, clock and reset configuration to the software driver.
Use DMA for substantial data transfers when setup cost is justified. Use register access for control and small transactions.
Define buffer ownership and the selected coherency mechanism. Apply required cache maintenance and memory ordering for that data path.
Check boot artifacts, hardware handoff, device tree, memory setup and peripheral addresses against the current FPGA design.
Plan keys, provisioning, authenticated images and recovery early. Test the device-specific flow before committing irreversible security settings.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.