.webp){kind=small}
Arria® V GT FPGA
Offers the lowest total power for mid-range applications and the lowest power transceivers for speeds up to 10.3125 Gbps.
Explore the Arria® V GZ FPGA
Arria V GX and GT FPGA offers the lowest total power for mid-range applications by using the 28 nm low power process to deliver the lowest static power, offering the lowest power transceivers for speeds up to 10.3125 Gbps, and providing superior fabric with hard IP designed to lower dynamic power.
Key Features
| Enhanced High-Speed Transceivers | Provides robust high-speed serial interfaces for communications and wireless infrastructure systems requiring reliable, high-bandwidth connectivity. |
| Simplified Multi-Standard Interface Design | Includes flexible clocking and jitter management to streamline design across multiple serial standards. |
| Low-Power Operation | Supports high-speed communication while maintaining low power consumption for energy-sensitive system designs. |
Benefits
Enhanced High-Speed Transceiver Support
Features enhanced transceiver capabilities for high-speed serial interfaces, supporting applications such as wireless base stations, test equipment, and wireline communications that require reliable, high-bandwidth connectivity.
Simplified Multi-Standard Interface Design
Offers signal integrity features and flexible clocking resources that simplify design challenges in systems operating across multiple serial standards.
Low-Power Communication Solutions
Maintains low power operation while enabling system designers to address advanced communication protocol requirements in space-constrained environments.
Product Package & Combination Selector
Start Design
Start your Arria V GT FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
10GBASE-R PHY FPGA IP
The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.
Nios® V Processors
By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Solutions
Arria® V GT FPGAs for Wireline
Arria® V GT FPGAs for Industrial
Arria® V GT FPGAs for Security
Resources
Documentation, downloads, videos, training, and support for Cyclone V ST FPGA
Common Questions
GT supports the higher documented serial rate. GX's 6.5536 Gbps capability is insufficient for a 10.3125 Gbps physical link.
Use the supported PHY-to-MAC interface and compatible clocking. The PHY handles physical coding; a MAC provides Ethernet frame processing.
Verify speed grade, package, channel availability and operating conditions in current GT documentation before finalizing the PCB.
Check input rate, reference clock, reset sequence and signal integrity, then inspect the supported PHY status indicators.
Use supported hard IP when it meets required features and interfaces. Compare resource and integration costs with a soft implementation.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.