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Cyclone® 10 GX FPGAs
The Cyclone 10 GX FPGA is built on a high-performance 20 nm process, offering a performance advantage for cost-sensitive applications.
Explore the Cyclone 10 GX FPGA
The Cyclone® 10 GX FPGA is a cost-sensitive, high-performance platform built on a 20 nm process. It delivers up to twice the performance of previous-generation Cyclone V FPGAs while combining programmable logic, high-bandwidth transceivers, DSP, memory interfaces, and hard PCIe IP for embedded systems that require efficient real-time processing and connectivity.
Key Features
| Transceivers | 12.5 Gbps chip-to-chip transceiver support, 6.6 Gbps backplane support along with hard PCI Express (PCIe) IP supporting PCIe 2.0. |
| External Memory Interface | High-performance external memory interface with up to 1,866 Mbps DDR3. |
| General Purpose I/O | Each I/O bank contains GPIOs featuring 1.434 Gbps LVDS I/Os and support a wide range of I/O interfaces. |
| Digital Signal Processing | IEEE 754-compliant hard floating-point digital signal processing (DSP) blocks. |
Benefits
Enhanced Core Architecture with High-Bandwidth Integrated Transceivers
Built on 20 nm process technology and programmable with the advanced Quartus design environment, achieve twice the performance of previous-generation Cyclone V FPGAs along with 12.5 Gbps chip-to-chip transceiver I/O and 6.6 Gbps backplane support.
Improved Efficiency and Timing Closure
The Adaptive Logic Module architecture – same as previous-generation FPGAs – allows the efficient implementation of logic functions, simplified conversion of intellectual property (IP) cores between the device generations, and improved timing closure in devices.
Advanced Power Saving
Cyclone 10 GX FPGAs offer a comprehensive set of advanced power-saving features with power-optimized MultiTrack routing and core architecture reducing power consumption.
Product Package & Combination Selector
Start Design
Start your Cyclone 10 GX FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration.
HDMI IP Core
The High-Definition Multimedia Interface (HDMI) IP provides support for next-generation video display interface technology.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus Prime Design Software v16.0 and above.
Solutions
Cyclone® 10 GX FPGAs for Industrial
Cyclone® 10 GX FPGAs for Medical
Cyclone® 10 GX FPGAs for Broadcast and Pro AV
Resources
Documentation, downloads, videos, training, and support for Cyclone 10 GX FPGA
Common Questions
Use GX when supported high-speed transceivers, memory bandwidth or floating-point DSP are needed for the camera and processing workload.
Include sensor writes, processing reads and display or host transfers, then account for memory efficiency and burst overlap.
The page lists different rates for different channel environments. Use the datasheet limit for the intended connection and selected grade.
Check sensor timing, FIFO occupancy, memory service rate and output backpressure. Measure each pipeline stage under peak traffic.
Use them when the algorithm requires suitable floating-point precision and the selected device has enough DSP resources.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.