Cyclone® 10 GX FPGA Developer Center

The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series.

Device Information

Interface Protocol

Design Planning

Design Entry

Simulation and Verification

Implementation and Optimization

Timing Analysis

On-Chip Debug

1. Device Information

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Cyclone® 10 GX
Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
Cyclone® 10 GX Transceiver PHY User Guide
Cyclone® 10 GX Device Datasheet
Cyclone® 10 GX Device Design Guidelines
Cyclone® 10 GX Device Errata and Design Guidelines
Cyclone® 10 GX Device Overview
Altera® I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Cyclone® 10 GX Device Family Pin Connection Guidelines
FPGA Advanced SEU Detection IP Core User Guide
Cyclone® 10 External Memory Interfaces IP User Guide
Cyclone® 10 External Memory Interfaces IP Design Example User Guide
FPGA OCT IP Core User Guide
FPGA GPIO IP Core User Guide
FPGA LVDS SERDES IP Core User Guide
FPGA Temperature Sensor IP Core User Guide
FPGA Parallel Flash Loader IP Core User Guide
FPGA ASMI Parallel II IP Core User Guide
FPGA ASMI Parallel IP Core User Guide
FPGA Remote Update IP Core User Guide
AN 496: Using the Internal Oscillator IP Core
AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families
AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software

Design Examples
Cyclone® 10 GX
Cyclone® 10 GX Design Examples on Design Store

Training and Videos
Cyclone® 10 GX
SEU Mitigation in Altera® FPGA Devices: Hierarchy Tagging

2. Interface Protocol

Documentation

User Guides
External Memory Interface
Cyclone® 10 External Memory Interfaces IP User Guide
Cyclone® 10 External Memory Interfaces IP Design Example User Guide
FPGA PHY Lite for Parallel Interfaces IP Core User Guide

User Guides / Device Overview / Device Datasheet / Application Notes
Ethernet
FPGA Triple-Speed Ethernet IP Core User Guide
FPGA Low Latency Ethernet 10G MAC User Guide
Cyclone® 10 GX Transceiver PHY User Guide
FPGA IP for Ethernet - Support Center
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 735: Altera® Low Latency Ethernet 10G MAC IP Core Migration Guidelines
AN 699: Using the Altera Ethernet Design Toolkit

User Guides
PCI Express*
Arria® 10 and Cyclone® 10 Avalon®-ST Interface for PCIe* User Guide
Arria® 10 or Cyclone® 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
Arria® 10 and Cyclone® 10 Avalon-MM Interface for PCIe User Guide
Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
FPGA IP for PCI Express – Support Center

User Guides
Digital Signal Processing (DSP)
FPGA CORDIC IP Core User Guide
BCH IP Core User Guide
FFT IP Core User Guide
FIR II IP Core User Guide
Viterbi IP Core User Guide
Turbo IP Core User Guide
Floating-Point IP Cores User Guide
High-Speed Reed-Solomon IP Core User Guide
Reed-Solomon II IP Core User Guide
NCO IP Core User Guide
Random Number Generator IP Core User Guide

User Guides
Embedded
Embedded Peripherals IP User Guide

User Guides
Audio and Video
FPGA SDI II IP Core User Guide

Design Examples
PCI Express*
Arria® 10 and Cyclone® 10 Avalon®-ST Hard IP for PCIe* Design Example User Guide
Arria® 10 and Cyclone® 10 Avalon -MM Interface for PCIe Design Example User Guide

Training and Videos
External Memory Interface
Guide for New External Memory Interface (EMIF) Spec Estimator

3. Design Planning

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Getting Started User Guide: Quartus® Prime Pro Edition
Platform Designer User Guide (Quartus® Prime Pro Edition)
DSP Builder for FPGAs
Cyclone® 10 GX Device Design Guidelines

Training and Videos
Fast & Easy I/O System Design with Interface Planner

4. Design Entry

Documentation

The Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started.

The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Handbook.

The Quartus® Prime design software also comes with High Level Synthesis Compiler which synthesizes a C function into an RTL implementation that is optimized for FPGA products.

User Guides / Device Overview / Device Datasheet / White Paper
Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis
Design Recommendations User Guide: Quartus® Prime Pro Edition
High Level Synthesis Compiler Getting Started Guide
High Level Synthesis Compiler User Guide
Platform Designer User Guide: Quartus® Prime Pro Edition
Scripting User Guide: Quartus® Prime Pro Edition
Advanced Synthesis Cookbook
High Level Synthesis Compiler Best Practices Guide
High Level Synthesis Compiler Reference Manual
High Level Synthesis Compiler Release Notes
Applying the Benefits of Network on a Chip Architecture to FPGA System Design

Design Examples
Platform Designer Pro Tutorial Design Example for Arria® 10 FPGA (.zip)
Platform Designer Tutorial Design Example for Arria® 10 FPGA (.zip)
Platform Designer Tutorial Design Example (.zip)
Quartus® Design Examples

Training and Videos
Using the Quartus® Prime Standard Edition Software: An Introduction
Introduction to Verilog HDL
Verilog HDL Basics
Verilog HDL Advanced
SystemVerilog with Quartus® Prime Design Software
VHDL Basics
Introduction to Platform Designer
Platform Designer in the Quartus® Prime Pro Edition Software
Creating a System Design with Platform Designer: Getting Started
Using the Quartus® Prime Pro Edition Synthesis Engine

Software Downloads
Download center for all versions of the Quartus® Prime software

5. Simulation and Verification

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Pro Edition User Guide: Third-party Simulation
Simulation Quick-Start for ModelSim*-Altera® FPGA Edition
Simulating the a8237 Model with the Visual IP Software
Avalon® Verification IP Suite User Guide
FPGA Software Installation and Licensing
Simulating the a8251 Model with the Visual IP Software
Simulating the Reed-Solomon Model with the Visual IP Software
Simulating the Turbo Encoder/Decoder Model with the Visual IP Software
AN 811: Using the Avery BFM for PCI Express* Gen3x16 Simulation on Stratix® 10 Devices
AN 720: Simulating the ASMI Block in Your Design
AN 351: Simulating Nios® II Processor Designs
AN 508: Cyclone® III Simultaneous Switching Noise (SSN) Design Guidelines
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
Simulating Altera® Devices with IBIS Models
Simulating FPGA Designs

Design Examples
Avalon® Verification IP Suite Design Example

Training and Videos
Advanced System Design Using Platform Designer: System Verification with System Console
Advanced System Design Using Platform Designer: Component & System Simulation
Design Software Online Demonstration
Verifying Memory Interfaces IP in Altera® FPGA Devices

Software Downloads
Quartus® Software

6. Implementation and Optimization

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Quartus® Prime Standard Edition Handbook Volume 2 Design Implementation and Optimization
Compiler User Guide: Quartus® Prime Pro Edition
Design Optimization User Guide: Quartus® Prime Pro Edition
Third-party Synthesis User Guide: Quartus® Prime Pro Edition
Design Constraints User Guide: Quartus® Prime Pro Edition
Block-Based Design User Guide: Quartus® Prime Pro Edition
Partial Reconfiguration User Guide: Quartus® Prime Pro Edition
Cyclone® 10 GX Device Design Guidelines

Training and Videos
Design Block Reuse in the Quartus® Prime Pro Software
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Design Partitioning
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Introduction
Incremental Block-Based Compilation in the Quartus® Prime Pro Software: Timing Closure & Tips

7. Timing Analysis

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Timing Analysis Overview
Timing Analyzer User Guide: Quartus® Prime Pro Edition
Quartus® Prime Timing Analyzer Cookbook
AN 366: Understanding I/O Output Timing for Altera® Devices
AN 471: High-Performance FPGA PLL Analysis with TimeQuest
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
AN 775: I/O Timing Information Generation Guidelines

Design Examples
Timing Analyzer Design Examples

Training and Videos
Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer
Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections
Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints
Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces
Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions
Getting Started with the TimeQuest Timing Analyzer
Timing Analysis: Lecture
Timing Analysis: Hands-on Labs
FPGA Timing Closure: Lecture
FPGA Timing Closure: Hands-On Lab

8. On-Chip Debug

Documentation

User Guides / Device Overview / Device Datasheet / Application Notes
Programmer User Guide: Quartus® Prime Pro Edition
Debug Tools User Guide: Quartus® Prime Pro Edition
Analyzing and Debugging Designs with System Console
FPGA Virtual JTAG (FPGA_virtual_jtag) IP Core User Guide
FPGA-Adaptive Software Debug and Performance Analysis
System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug
ByteBlaster II Download Cable User Guide
FPGA USB Download Cable User Guide
FPGA Download Cable II User Guide
EthernetBlaster Communications Cable User Guide
BSDL Support
AN 827: Unified Tool for Generating Programming Files
AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems,Design files
AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer
AN 799: Quick Arria® 10 Design Debugging Using Signal Probe and Rapid Recompile
AN 693: Remote Hardware Debugging over TCP/IP for Altera SoC
AN 541: SerialLite II Hardware Debugging Guide
AN 543: Debugging Nios® II Software Using the Lauterbach Debugger
AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench
AN 624: Debugging with System Console over TCP/IP

Training and Videos
Debugging JTAG Chain Integrity
On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices
JTAG Chain Debugger Tool
Quick Signal Tapping with SignalProbe in the Quartus® II Software

FPGA Wiki
Development Boards and Kits

Software Downloads
FPGA Programming Software
Cable and Adapter Drivers Information
Quartus® Prime Software Stand-Alone Programmer

Knowledge Base Solution

Search the Knowledge Base for Cyclone® 10 GX Devices