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Cyclone® V ST
Cyclone V ST SoC FPGA is the FPGA industry’s low cost and power for 6.144 Gbps transceiver applications.
Explore the Cyclone V ST SoC FPGA
The Cyclone V ST SoC FPGA is a low-cost, power-efficient platform for applications requiring up to 6.144 Gbps transceiver performance. Built on TSMC's 28 nm low-power process, it combines a dual-core Arm Cortex-A9 MPCore processor system with programmable FPGA logic, hard IP, and variable-precision DSP resources in a single device.
Key Features
| Embedded Memory Blocks | M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC). Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory. |
| General-purpose I/Os | 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter. 400 MHz/800 Mbps external memory interface. On-chip termination (OCT). 3.3 V support with up to 16 mA drive strength. |
| External Memory Interface | In the Cyclone® V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices. |
| Hard Processor System (HPS) | The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multiport SDRAM memory controller. |
Benefits
Do More with Less Power, Design Time, and Cost
Built on TSMC's 28 nm low-power (28LP) process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more.
Logic Integration and Differentiation Capabilities
It offers an 8-input adaptive logic module (ALM) and variable-precision digital signal processing (DSP) blocks, allowing up to 13.59 megabits (Mb) of embedded memory.
Hard processor system (HPS) with integrated ARM® Cortex®-A9 MPCore processor
Tight integration of a dual-core ARM® Cortex®-A9 MPCore processor, hard IP, and an FPGA in a single Cyclone V system-on-a-chip (SoC). It supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric.
Product Package & Combination Selector
Start Design
Start your Cyclone V ST FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
ARM Cortex-A9 Processor IP
Provides embedded processing for hardware-software integration.
DSP Block IP
Accelerates complex filtering and signal processing workloads.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Solutions
Cyclone® V ST FPGAs for Industrial
Cyclone® V ST FPGAs for Transportation
Cyclone® V ST FPGAs for Medical
Resources
Documentation, downloads, videos, training, and support for Cyclone V ST FPGA.
Common Questions
Choose ST when supported CPRI configurations require up to 6.144 Gbps. Compare part-specific resources and other protocol limits separately.
Use a documented sequence for fabric configuration, clocks, resets and control registers. Wait for valid link status before enabling traffic.
The physical link rate does not guarantee software can process every byte. Budget DMA, memory and CPU work separately.
Check driver writes, clock/reset ownership and runtime configuration changes. Compare register state before and after software initialization.
Use required maintenance when the configured DMA path is not coherent. Define CPU/device ownership and memory ordering for each buffer.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.