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Stratix® 10 TX
Transceiver bandwidth with up to 58 Gbps PAM4 for 400G and beyond.
Explore the Stratix® 10 TX FPGA
The Stratix 10 TX FPGA meets rigorous demands with the newly developed PAM4 technology, enabling up to 57.8 Gbps in up to 144 transceiver lanes, meeting bandwidth needs of 5 GB communications, cloud computing, network functions virtualization, and optical transport networks.
Key Features
| Hyperflex® FPGA Architecture | At the heart of the HPS is a highly efficient quad-core Arm Cortex*-A53 processor cluster, and this processor is optimized for ultra-high performance per watt, which reduces power consumption. The HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals. |
| Transceivers | The device offers up to 144 total full-duplex transceiver channels providing continuous data rates from 1 Gbps to 28.9 Gbps in NRZ mode and 2 Gbps to 57.8 Gbps in PAM4 mode for chip-to-chip, chip-to-module, and backplane applications. |
| Hard Processor System (HPS) | HPS performs better with an integrated quad-core 64-bit Arm Cortex-A53 processor while enabling system-wide hardware virtualization capabilities by adding a system memory management unit on selected Stratix 10 TX devices. |
Benefits
Enabling the Future of Networking
Stratix 10 TX devices deliver dual-mode modulation, 57.8 Gbps PAM4, and 28.9 Gbps NRZ, enabling early adoption of next-generation data infrastructure and backward compatibility. With transceivers PAM4 capabilities, build next-generation communication and networking infrastructure that supports 50GE, 100GE, 200GE, 400GE, and terabit applications, allowing larger data transmission capacity than binary modulation.
Ethernet Hard IP Solution
The devices deliver power savings and latency time to market with hard intellectual property (IP) solutions for Ethernet. The following hard IP(s) are available with the Stratix 10 TX: Deterministic latency support for Common Public Radio Interface (CPRI) PCS, Option to bypass MAC, PCS, FEC, OTN PCS Mode, and the following 10GBASE-R/CR/KR, 25GBASE-R/CR/KR, 100GBASE-R4/CR4/KR4, 100GBASE-R2/CR2/KR2 Forward Error Correction (FEC).
Power Management Delivering Increased Power Saving
The advanced 14 nm tri-gate process technology and Hyperflex core architecture enable Hyper-Folding, power gating, and optional power reduction techniques to reduce total power consumption compared to previous generation high-performance Stratix V devices. The device also features low-power transceivers and includes several hard IP blocks that reduce logic resources while delivering power savings compared to soft implementations.
Product Package & Combination Selector
Start Design
Everything you need to begin a Stratix 10 TX FPGA design.
DDR5 and DDR4, LPDDR5, and LPDDR4 External Memory Interfaces FPGA IP
When integrated with Altera® FPGAs, these memory technologies enable faster data processing and more efficient power usage for a wide range of applications including networking, cloud, and edge.
Stratix 10 FPGA H-Tile Hard IP for Ethernet
This IP core configures the transceivers to implement the relevant specification for your IP core variation.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Solutions
Stratix 10 TX FPGAs for Wireline
Stratix 10 TX FPGAs for Wireless
Stratix 10 TX FPGAs for Test and Measurement
Resources
Start developing with Stratix 10 TX FPGAs with these resources.
Training & Learning
Common Questions
Use supported PAM4 when required bandwidth and channel margins justify it. Compare signal integrity, FEC and endpoint compatibility with NRZ.
PAM4 carries two bits per symbol. Protocol overhead and error correction further reduce usable application payload throughput.
Use supported MAC, PCS or FEC bypass only when replacement logic and endpoint requirements are clearly defined and verified.
Check signal levels, linearity, equalization, clock quality and supported FEC settings. PAM4 needs different margins than binary signaling.
Only after confirming the exact device includes an HPS. A copied processor paragraph is insufficient evidence for device selection.