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FPGA Development Tools & Software
Incremental Optimization
Incremental Optimization in Quartus® Prime Pro Edition design software provides a faster, more controlled path to design sign-off by dividing the traditional fitter process into smaller stages.
Overview
The incremental optimization capability in the Quartus® Prime Design Software Pro Edition software offers a fast methodology to converge to design sign-off. The traditional fitter stage is divided into finer stages for more control over the flow in the Quartus® Prime Pro Edition software:
- Plan stage allows legal placement and clock planning, along with timing analysis on preliminary I/O and HSSI to FPGA fabric transfers.
- Placement stage enables timing analysis before proceeding to the Route stage. The Placement stage is split into an Early Placement stage and a final placement stage:
- Perform timing analysis after the Early Placement stage while the rest of the flow is still running
- Chip planner provides a visual view of the Early Placement stage Route is split into.
- Route and Post-Route stages for faster design convergence.
- 3-corner timing analysis after route and 4-corner timing analysis after post-route reduces compile time.
- The post-route stage offers an Engineering Change Order (ECO)-like flow where setup and hold failures are automatically fixed, thus reducing compile time.
- High-speed or low-power tile optimization is performed in the Post-Route stage.
Resources
Training & Learning
Common Questions
Incremental Optimization is a capability in Quartus Prime Pro Edition that provides a faster methodology for converging on design sign-off.
It divides the traditional fitter stage into finer stages, giving designers more control over placement, clock planning, routing, and timing analysis.
The Plan stage supports legal placement and clock planning, while the Placement stage enables timing analysis before routing. Early Placement also allows designers to analyze timing while the rest of the flow continues, with Chip Planner providing a visual view of the placement.
The Route stage is divided into Route and Post-Route stages. Three-corner timing analysis after routing and four-corner timing analysis after post-route optimization help reduce compile time.
The Post-Route stage provides an ECO-like flow that can automatically fix setup and hold failures. It also supports high-speed or low-power tile optimization.
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