Aerospace and Defense Design

To help new users comprehend Direct RF FPGA capabilities quickly and allow out-of-the-box evaluation capability, Altera developed an analog-to-digital converter (ADC) or digital-to-analog converter (DAC) cockpit design example. This design features a graphical user interface (GUI) to explore and configure the analog tile blocks with various settings. These include configuring the decimation or interpolation modes of up/down converters, the center frequency of course and fine tuners, setting loopback modes, sample rate, etc.

Altera developed a wideband channelizer design example to showcase Direct RF FPGA capabilities. This design features a polyphase filter bank developed using a DSP Builder design tool oriented for DSP developers. The analog-to-digital converter (ADC) data is streamed into the channelizer block, which includes a prototype polyphase filter and 64 64-phase FFT block.

Digital Time Delay Beamforming offers arbitrary angular resolution, simultaneous beams at different angles, and makes no compromise in quality.

This design features a super sample rate fractional delay resampler filter in the time delay engine developed using the DSP Builder design tool oriented for DSP developers. There are four instances of the time delay engine to support four simultaneous beams, where each beam is independent and controlled separately.

To showcase Direct RF FPGA synchronization capability, Altera developed a multiple-device synchronization design example. This design demonstrates the deterministic latency link between two analog-to-digital converter (ADC) or digital-to-analog converter (DAC) nodes by using the JESD204C subclass1 protocol, latency alignment, and phase alignment between different ports in local and remote devices.

The wideband and Agility features design example demonstrates the ability of frequency hopping in Direct RF FPGA and how this capability, combined with wideband monitoring, can be a significant advantage for certain applications.

FPGA AI Suite can be used in FPGA design to process a real-time stream of an analog signal. Altera developed a waveforms classification example that uses a specially trained neural network to classify RF signal modulation type. 

In this design example, the MVDR algorithm is implemented. The MVDR adaptive beamforming uses sample-matrix inversion (SMI) methods, which determine the antenna array weights directly from observation. The adaptive solution is found using a QR decomposition linear solver implemented in floating-point mathematics on the FPGA. Real-time data is sampled using an array of integrated analog/digital converters and processed using IP developed using the DPC++ language.

Digital Phase Shift Beamforming enables precise, dynamic beam steering with arbitrary angular resolution and multiple simultaneous beams.

This design implements ten independent phase-shift engines developed in DSP Builder, using the Agilex® 9 DirectRF SoC FPGA’s Medium-Band ADCs and DSP capabilities. Using 16 RX and 4 Feedback ADCs with channel synchronization, it demonstrates coherent, high-performance beamforming visualized through a MATLAB® GUI.

The example demonstrates a high-throughput, low-latency data transfer architecture on the Altera® Agilex® 9 Direct RF FPGA, utilizing integrated A-Tile data converters, F-Tile transceivers, and external memory interfaces. An AXI4-Stream crossbar provides flexible, reliable on-chip communication across 24 bi-directional TX/RX channels linking A-Tiles, F-Tiles, and memory. Real-time dataflow control is enabled through crossbar adapter modules supporting AVST-to-AXI-ST conversion and metadata routing, while a MATLAB host GUI allows dynamic hardware interaction. The system achieves an average latency of 134 ns and throughput of 192 GB/s, highlighting efficient low-latency streaming performance.

DOA estimation is achieved using an AI-based approach, where a neural network (NN) is trained to infer DOA directly from the input covariance matrix. Additional neural networks perform signal detection and estimate the number of active sources. All NNs are deployed on the FPGA for real-time inference.

Marine Radar design example shows implementation of complex digital signal processing pipeline on Agilex 5 FPGA. The implementation is done using DSP Builder tool that accelerates designer's productivity and delivers best-in-class DSP performance on the FPGA.

This design example demonstrates the efficient implementation of a synthesis filter bank, known as an inverse-channelizer. It shows a parametrizable implementation in DSP Builder that can be adjusted to end-user applications. The operation of the filter bank is shown in cognitive radio application, where perfect reconstruction of the signal is required.

This is a subset of a wideband SSR oversampling channelizer. The implementation architecture of an oversampling channelizer can be very different depending on the input sample rate, number of channels, and number of overlapping samples. In this architecture, the number of FFT channels is low, and the number of overlapping samples is less than the number of parallel paths. Overlapping inputs happen across parallel paths, thus the term 'spatial overlapping.'

This design features a polyphase filter bank developed using the DSP Builder design tool oriented for DSP developers. Data from the On-chip Signal Generator is streamed into a Channelizer block that includes the Commutator, Polyphase Filters, Circular Shifter, and FFT block. The captured output of the Channelizer is uploaded to the host and presented to viewers while showing some key signal quality metrics. Oversampled Channelizer design includes an On-chip Signal Generator, which can provide programmable stimulus to the Channelizer system, making the design example run without an external signal generator and ADC.

The MVDR adaptive beamformer example design shows an efficient implementation of adaptive beamforming on FPGAs. The adaptive beamformer achieves optimal signal quality from the desired direction while suppressing interference from the undesired direction. MVDR is based on the sample matrix inversion method, where the beamforming weights are calculated based on direct observation of the environment.

Channelizer is a wideband receiver that splits a wide bandwidth into individual bands of interest. As a result of processing gain, low signal-to-noise ratio (SNR) signals can be reliably detected in individual subchannels.

The radar waveform classification example design is built to recognize unique micro-Doppler signatures of different targets using a convolution neural network (CNN) model.

Synthetic Aperture Radar (SAR) is a technique used in modern radars to acquire high-resolution images of scenes. Altera FPGAs are enabling such technology even under tight SWaP constrains.

Semantic Segmentation is used in a variety of self-navigating robotic applications. The application is to classify the type of object that each pixel in the image belongs to. This example shows the detection and segmentation of houses from overhead imagery.

Monobit Digital RF Memory design example demonstrates the use of FPGAs with integrated high-speed transceivers as a wideband front-end stage.

The Partition-Based Security design example demonstrates a secure way of assigning security keys to multiple encrypted partial regions in the FPGA.

This design example demonstrates pulse doppler processing. In a typical radar application, Doppler frequencies must be calculated and identified. This is done by calculating FFT across multiple coherent radar pulses. Due to the inherent write/read pattern of dynamic memories, the corner turn operation is inefficient. This design shows how to mitigate the throughput bottleneck caused by the corner turn.

This reference design includes generating a Wideband Gaussian Noise signal using a poly-phase approach. Subsequent signal processing enables you to populate only desired spectral bands with custom-defined magnitudes for each band.

The FFT beamforming demo generates multiple beams simultaneously for spatial filtering. This translates to better performance, which is an essential requirement for real-time systems.

The QR Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. QR-based algorithm has good numerical stability and can solve rectangular, over-determined equation systems. The algorithm is one of the first complex floating-point reference designs highlighting feasibility and performance of floating-point IP on FPGA.

The Extended Kalman Filter (EKF) is implemented on the Cyclone V SoC FPGA. It efficiently utilizes a hybrid architecture, where a portion of the algorithm is offloaded to the FPGA fabric to increase overall system performance and offload the Arm* processor.

The Cholesky Decomposition Solver design example is a parameterizable implementation designed to solve various matrix sizes. Cholesky-based algorithm can solve private case of square equation system, in more efficient way than other algorithms like QR. The algorithm is one of the first complex floating-point design examples highlighting feasibility and performance of floating-point IP on FPGA.

The Time Delay Beamforming design example is implemented in the Stratix V DSP Development Kit. True time delay is achieved through a fractional delay filter with arbitrary fine resolution. The design example covers a simple but complete transmit and receive pulsed radar system with 32 phased array elements.

In a typical pulsed radar, Pulse Compression correlates receive signal with a known waveform to increase the range resolution and SNR. This design example demonstrates Pulse Compression with Overlap-and-Save technique.