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Device Configuration Support Center

Device Configuration Support Center provides documentation and training to select a design, and implement configuration features.

1. Device Specific Configuration Details 2. Configuration Schemes and IP 3. Advanced Configuration Features 4. Quartus® Prime Software Design Flow 5. Board Design 6. Debug Supported Flash Memory Devices (Configuration Devices) Supported Third Party Configuration Devices in SDM Devices Supported Third Party Configuration Devices in Control-Block based Devices Design Examples and Reference Designs Training Courses and Videos
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The Device Configuration Support Center provides resources for Agilex® 7, Agilex® 5, Agilex® 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.

You will find information on how to select, design, and implement configuration schemes and features. There are also guidelines on how to bring up your system and debug the configuration links. This page is organized into categories that align with a configuration system design flow from start to finish.

Get additional support for Agilex® 7 System Architecture, Agilex® 5 System Architecture and the Agilex® 3 System Architecture, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

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1. Device Specific Configuration Details

Table 1 - Configuration Schemes and Features Overview

Device FamilyConfiguration SchemesConfiguration Features
 SchemeData WidthMax Clock RateMax Data RateConfiguration Via ProtocolDesign SecurityPartial Reconfiguration (2)Decompression SupportRemote System UpdateSingle Event Upset
Agilex® 7Avalon® Streaming32 bits125 MHz4000 MbpsN/A√√√Parallel Flash Loader II IP core√
16 bits125 MHz2000 Mbps√√
8 bits125 MHz1000 Mbps√√
Active Serial (AS)4 bits166(1) MHz664 Mbps√√√√√
JTAG1 bit30 MHz30 MbpsN/A√√N/A√
Agilex® 5Avalon® Streaming  16 bits125 MHz2000 MbpsN/A√√√Parallel Flash Loader II IP core√
8 bits125 MHz1000 Mbps√√
Active Serial (AS)4 bits166(1) MHz664 Mbps√√√√√
JTAG1 bit30 MHz30 MbpsN/A√√N/A√
Agilex® 3Avalon® Streaming16 bits125 MHz2000 MbpsN/A√√√Parallel Flash Loader II IP core√
8 bits125 MHz1000 Mbps√√
Active Serial (AS)4 bits166(1) MHz664 Mbps√√√√√
JTAG1 bit30 MHz30 MbpsN/A√√N/A√
Stratix® 10Avalon®-ST32 bits125 MHz4000 MbpsN/A√√√Parallel Flash Loader II IP core√
16 bits125 MHz2000 Mbps√√
8 bits125 MHz1000 Mbps√√
Active Serial (AS)4 bits125(1) MHz500 Mbps√√√√√
JTAG1 bit30 MHz30 MbpsN/A√√

N/A

√
Arria® 10Configuration via HPS32 bits100 MHz3200 MbpsN/A√√√via HPS√
16 bits100 MHz1600 Mbps√
Fast Passive Parallel (FPP)32 bits100 MHz3200 MbpsN/A√√Parallel Flash Loader IP core√
16 bits100 MHz1600 Mbps√
8 bits100 MHz800 Mbps√
Active Serial (AS)4 bits100 MHz400 Mbps√√√(3)√√
1 bit100 MHz100 Mbps√
Passive Serial (PS)1 bit100 MHz100 MbpsN/A√√(3)Parallel Flash Loader IP core√
JTAG1 bit33 MHz33 MbpsN/A √(3)

N/A

√
Cyclone® 10 GXFast Passive Parallel (FPP)32 bits100 MHz3200 MbpsN/A√√√Parallel Flash Loader IP core√
16 bits100 MHz1600 Mbps√
8 bits100 MHz800 Mbps√
Active Serial (AS)4 bit100 MHz400 Mbps√√√(3)√√
1 bits100 MHz100 Mbps√
Passive Serial (PS)1 bit100 MHz100 MbpsN/A√√(3)Parallel Flash Loader IP core√
JTAG1 bit33 MHz33 MbpsN/AN/A√(3)

N/A

√
Cyclone® 10 LPFast Passive Parallel (FPP)8 bits66(4)/100(6) MHz528(4)/800(6) MbpsN/AN/AN/A√Parallel Flash Loader IP core√
Passive Serial (PS)1 bit66(4)/133(5) MHz66(4)/133(5) MbpsN/AN/AN/AParallel Flash Loader IP core√
Active Serial (AS)1 bit40 MHz40 MbpsN/AN/AN/A√√
JTAG1 bit25 MHz25 MbpsN/AN/AN/A

N/A

√
MAX® 10     √ √√ 
Stratix® V     √ √√ 
Arria® V     √ √√ 
Cyclone® V     √ √√ 
Stratix® IV     √ √√ 
Cyclone® IV E     - √√ 
Cyclone® IV GX     - √√ 
Stratix® III     √ √√ 
Cyclone® III LS     √ √√ 
Cyclone® III     - √√ 
Arria® II GX     √ √√ 
Cyclone® II     - √- 

Notes:

  1. The maximum clock rate when using OSC_CLK_1 as configuration clock source. The maximum clock rate reduces if you use the internal oscillator as the configuration clock source, during SmartVID operation, or when the device is in user mode.
  2. You can perform partial reconfiguration after the device is fully configured. For more information, refer to the Partial Reconfiguration User Guide.
  3. Partial configuration can be performed only when it is configured as internal host.
  4. Supply voltage for internal logic, VCCINT = 1.0 V.
  5. Supply voltage for internal logic, VCCINT = 1.2 V.
  6. Supply voltage for internal logic, VCCINT = 1.2 V. Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only.

2. Configuration Schemes and IP

Configuration User Guides

Agilex® 7 Devices

  • Agilex® 7 Configuration User Guide

Agilex® 5 Devices

  • Device Configuration User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Device Configuration User Guide Agilex® 3 FPGAs and SoCs

Stratix 10® Devices

  • Stratix® 10 Configuration User Guide

Configuration via HPS

Configure the FPGA portion of the SoC device by utilizing Hard Processor System (HPS)

Agilex® 7 Devices
 

  • Agilex® 7 Hard Processor System Technical Reference Manual

Agilex® 5 Devices

  • Hard Processor System Technical Reference Manual: Agilex® 5 SoCs

Agilex® 3 Devices

  • Hard Processor System Technical Reference Manual: Agilex® 3 SoCs

Stratix® 10 Devices

  • Stratix® 10 SoC FPGA Boot User Guide
     
  • Stratix® 10 Hard Processor System Technical Reference Manual

Arria® 10 Devices

  • Arria® 10 SoC FPGA Boot User Guide
     
  • Arria® 10 Hard Processor System Technical Reference Manual

Fast Passive Parallel

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

  • FPGA Parallel Flash Loader IP Core User Guide

Active Serial

Agilex® 7 Devices

  • Agilex® 7 Configuration User Guide

Agilex® 5 Devices

  • Device Configuration User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Device Configuration User Guide Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Configuration User Guide
     

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook
     

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
     

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook
     

Additional Resources:

  • AN 370: Using the FPGA Serial Flash Loader IP Core with the Quartus® Prime Software
     
  • AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming

Passive Serial

Arria® 10 GX Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

  • FPGA Parallel Flash Loader IP Core User Guide

JTAG

Agilex® 7 Devices

  • Agilex® 7 Configuration User Guide
  • AN 936: Executing SDM Commands via JTAG Interface

Agilex® 5 Devices

  • Device Configuration User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Device Configuration User Guide Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Configuration User Guide
  • AN 936: Executing SDM Commands via JTAG Interface

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

Additional Resources:

  • Cable and Adapter Drivers Information
  • AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
  • Programming Support for Jam STAPL Language
  • AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration

Configuration via Protocol (CvP)

Agilex® 7 Devices

  • Agilex® 7 Device Configuration via Protocol (CvP) Implementation User Guide

Agilex® 5 Devices

  • Configuration via Protocol (CvP) Implementation User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Configuration via Protocol (CvP) Implementation User Guide: Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Arria® 10 Devices

  • Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
     
  • Arria® 10 Software Driver Code

Cyclone® 10 GX Devices

  • Cyclone® 10 GX CvP Initialization over PCI Express User Guide
     
  • Cyclone® 10 Software Driver Code

3. Advanced Configuration Features

Device Security

FPGAs can decrypt a configuration bitstream using the advanced encryption standard (AES) algorithm. When using the design security feature, a security key is stored in the FPGA. To successfully configure an FPGA that has the design security feature enabled, you must configure the FPGA with a configuration file that was encrypted using the same security key. Some FPGAs offer both volatile and non-volatile security key storage. The volatile security key storage requires battery back-up but enables the security key to be updated. The non-volatile security key can be stored in non-volatile memory inside the device and does not require battery back-up for storage.

Agilex® Family and Stratix® 10 Devices

  • Security Overview for SDM-Based FPGA Devices

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
     

Additional Resources:

AN 556: Using the Design Security Features in FPGAs

AN 512: Using the Design Security Feature  - Stratix III

AN 341: Using the Design Security Feature -  Stratix II

Partial Reconfiguration

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA resources. PR enables the implementation of more complex FPGA systems.

Quartus® Prime Pro Edition User Guide: Partial Reconfiguration - Agilex® 7, Agilex® 5, and Agilex® 3 devices, Stratix® 10 devices, Arria® 10 devices, Cyclone® 10 GX devices

Quartus® Prime Standard Edition User Guide: Partial Reconfiguration - Stratix® V device family and Cyclone® V devices whose part number ends in "SC", for example, 5CGXFC9E6F35I8NSC.

Agilex® Family Devices

  • Partial Reconfiguration Solutions IP User Guide

Stratix® 10 Devices

  • Partial Reconfiguration Solutions IP User Guide
     
  • AN 825: Partially Reconfiguring a Design on Stratix® 10 GX FPGA Development Board
  • AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix® 10 GX FPGA Development Board
  • AN 818: Static Update Partial Reconfiguration Tutorial for Stratix® 10 GX FPGA Development Board
  • AN 819: Partial Reconfiguration over PCI Express* Reference Design for Stratix® 10 Devices
  • AN 820: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Stratix® 10 Devices

Arria® 10 Devices

  • Partial Reconfiguration Solutions IP User Guide
     
  • Arria® 10 CvP Initialization and Partial Reconfiguration via Protocol User Guide
  • AN 817: Static Update Partial Reconfiguration Tutorial for Arria® 10 GX FPGA Development Board
  • AN 798: Partial Reconfiguration with the Arria® 10 HPS
  • AN 797: Partially Reconfiguring a Design on Arria® 10 GX FPGA Development Board
  • AN 784: Partial Reconfiguration over PCI Express Reference Design for Arria® 10 Devices
  • AN 805: Hierarchical Partial Reconfiguration of a Design on Arria® 10 SoC Development Board
  • AN 806: Hierarchical Partial Reconfiguration Tutorial for Arria® 10 GX FPGA Development Board
  • AN 813: Hierarchical Partial Reconfiguration over PCI Express Reference Design for Arria® 10 Devices

Cyclone® 10 GX Devices

  • Partial Reconfiguration Solutions IP User Guide
     

Additional Resources:

  • Quartus® Prime Pro Edition User Guide: Partial Reconfiguration
     
  • Quartus® Prime Standard Edition User Guide: Partial Reconfiguration
  • Partial Reconfiguration Support Page
  • Quartus® Prime Standard Edition User Guide: Partial Reconfiguration FPGA IP
  • Partial Reconfiguration IP Core User Guide

Decompression Support

Some FPGAs support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to the FPGA. During configuration, the FPGA decompresses the bitstream in real time and configures its CRAM cells.

Remote System Update

Altera devices have dedicated remote system upgrade circuitry. Soft logic (either the Nios® V embedded processor or user logic) implemented in the device that can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry helps to avoid system downtime.

Agilex® 7 Devices

  • Agilex® 7 Configuration User Guide

Agilex® 5 Devices

  • Device Configuration User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Device Configuration User Guide Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Configuration User Guide
     
  • Example of Tcl script
  • Stratix® 10 SoC Remote System Update (RSU) User Guide

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
     

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook
     

Additional Resources:

  • Remote Update FPGA IP Core User Guide
     

Single Event Upset (SEU) Mitigation

Agilex® 7 Devices

  • Agilex® 7 SEU Mitigation User Guide

Agilex® 5 Devices

  • SEU Mitigation User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • SEU Mitigation User Guide: Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 SEU Mitigation User Guide

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook
  • AN 737: SEU Detection and Recovery in Arria® 10 Devices
  • Mitigating Single Event Upsets in Arria® 10 Devices (Video)

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook
     

Additional Resources:

  • Introduction to Single-Event Upsets
  • Advanced SEU Detection FPGA IP User Guide
  • FPGA Fault Injection IP Core User Guide
  • Understanding Single Event Functional Interrupts in FPGA Designs
  • SEU Mitigation in FPGA Devices: Hierarchy Tagging (Video)

Flash Access IP

Agilex® 7 Devices

  • Mailbox Client FPGA IP User Guide
  • Mailbox Avalon ST Client FPGA IP User Guide
  • AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices

Agilex® 5 and Agilex® 3 Devices

  • Mailbox Client FPGA IPs User Guide

Stratix® 10 Devices

  • Mailbox Client FPGA IP User Guide
     
  • Serial Flash Mailbox Client FPGA IP User Guide
  • AN 932: Flash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices

Arria® 10 Devices

  • Generic Serial Flash Interface FPGA IP Core User Guide
     
  • Active Serial Memory Interface (ASMI) Parallel FPGA IP Core User Guide
  • Active Serial Memory Interface (ASMI) Parallel II FPGA IP Core User Guide
  • AN 720: Simulating the ASMI Block in Your Design

Cyclone® 10 GX Devices

  • Generic Serial Flash Interface FPGA IP Core User Guide
     
  • Active Serial Memory Interface (ASMI) Parallel I FPGA IP Core User Guide
  • Active Serial Memory Interface (ASMI) Parallel II FPGA IP Core User Guide
  • AN 720: Simulating the Active Serial Memory Interface (ASMI) Block in Your Design

Cyclone® 10 LP Devices

  • Generic Serial Flash Interface FPGA IP Core User Guide
     
  • Active Serial Memory Interface (ASMI) Parallel FPGA IP Core User Guide
  • Active Serial Memory Interface (ASMI) Parallel II FPGA IP Core User Guide
  • AN 720: Simulating the Active Serial Memory Interface (ASMI) Block in Your Design

Chip ID IP

Agilex® 7 Devices

  • Mailbox Client FPGA IP User Guide
     
  • Mailbox Avalon ST Client FPGA IP User Guide

Agilex® 5 and Agilex® 3 Devices

  • Mailbox Client FPGA IPs User Guide

Stratix® 10 Devices

  • Chip ID FPGA IP Cores User Guide
     

Arria® 10 Devices

  • Chip ID FPGA IP Cores User Guide
     

Cyclone® 10 GX Devices

  • Chip ID FPGA IP Cores User Guide
     

4. Quartus® Prime Software Design Flow

Table 2 - Device Configuration Setting and Programming Files Generation Flow

Topic Description
General Setting
  • General page of the Device and Pin Options dialog box in the Quartus Prime Software.
  • Specify the device options. These options are independent on the configuration scheme.
Configuration Setting
  • Configuration page of the Device and Pin Options dialog box in the Quartus Prime Software.
  • Specify the Device Configuration scheme, Configuration Device setting and Configuration Pin setting.
Programming Files Setting
  • Programming Files page of the Device and Pin Options dialog box in the Quartus Prime Software.
  • Select the programming file format to generate. Selecting the programming file in this page is optional, user is recommended to use the Convert Programming File or Programming File Generator to convert/generate the type of programming file for the used of selected configuration scheme.
Others Optional Advanced Feature Setting
  • Error Detection CRC, CvP Settings and Partial Reconfiguration page of the Device and Pin Options dialog box in the Quartus Prime Software.
  • Error Detection CRC page - Specify whether error detection is used and the rate at which it is checked.
  • CvP Settings page - Specify the type of CvP settings.
  • Partial Reconfiguration page - Specify Partial Reconfiguration settings.
Generate Configuration and Programming Files
  • Once design compilation is completed, the Convert Programming Files or Programming File Generator is the tool in Quartus Prime Software to convert/generate the type of programming file for selected configuration scheme or configuration feature.

Where Can I Find Information on Device Configuration Settings and Configuration & Programming Files Generation?

Agilex® 7 Devices

  • Agilex® 7 Configuration User Guide

Agilex® 5 Devices

  • Device Configuration User Guide: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Device Configuration User Guide Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Configuration User Guide
     

Arria® 10 Devices

  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
     

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook
     

5. Board Design

Where Can I Find Information on Device Configuration Design Guidelines?

Agilex® 7 Devices

  • AN 886: Agilex® 7 Device Design Guidelines

Agilex® 5 Devices

  • Device Design Guidelines: Agilex® 5 FPGAs and SoCs
  • Cyclone® V to Agilex® 5 Device Migration Guide

Agilex® 3 Devices

  • Device Design Guidelines: Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Device Design Guidelines
     

Arria® 10 Devices

  • AN 738: Arria® 10 Device Design Guidelines
     
  • AN 763: Arria® 10 SoC Device Design Guidelines

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Device Design Guidelines

Where Can I Find Information on the Connection Guidelines for Configuration Pin?

Agilex® 7 Devices

  • Agilex® 7 Device Family Pin Connection Guidelines

Agilex® 5 Devices

  • Pin Connection Guidelines: Agilex® 5 FPGAs and SoCs

Agilex® 3 Devices

  • Pin Connection Guidelines: Agilex® 3 FPGAs and SoCs

Stratix® 10 Devices

  • Stratix® 10 Device Family Pin Connection Guidelines
     

Arria® 10 Devices

  • Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines
     

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Device Family Pin Connection Guidelines
     

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Device Family Pin Connection Guidelines
     

Where Can I Find Information on Configuration Specifications?

The configuration specification in the device datasheet specifies the following specifications:

  • Timing specifications for configuration control pins
     
  • Timing/Performance specifications for each of the supported configuration scheme
  • Configuration bit stream sizes

Agilex® 7 Devices

  • Agilex® 7 Device Datasheet

Agilex® 5 Devices

  • Agilex® 5 FPGAs and SoCs Device DataSheet

Agilex® 3 Devices

  • Agilex® 3 FPGAs and SoCs Device DataSheet

Stratix® 10 Devices

  • Stratix® 10 Device Datasheet
     

Arria® 10 Devices

  • Arria® 10 Device Datasheet
     
  • Arria® 10 Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 GX Devices

  • Cyclone® 10 GX Device Datasheet
     
  • Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

Cyclone® 10 LP Devices

  • Cyclone® 10 LP Device Datasheet
     
  • Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook

6. Debug

Configuration debugger tool helps you debug programming and configuration issues. This tool is supported in Quartus® Prime Pro Edition Programmer version 21.3 onwards.

AN 955: Programmer’s Configuration Debugger Tool

FPGA Configuration Troubleshooter

Agilex® 7 and Stratix® 10 FPGA System Console Debugging Tool Using JTAG

  • AN 936: Executing SDM Commands via JTAG Interface

Stratix® 10 FPGA SDM Debug Toolkit helps you debug your configuration issues.

  • It is available in Quartus Prime Pro Edition software v18.1 and onwards.

Searching a tool to debug configuration failures / design security / error detection cyclic redundancy check (CRC) on Arria® 10 devices?

  • To get this configuration diagnostic tool, please contact your Altera sales representative.
     

You can use this troubleshooter, fault tree analysis or troubleshooting guides to identify possible configuration failure causes.

  • FPGA Configuration Troubleshooter
  • Configuration Fault Tree Analysis
  • Troubleshooting Guides

Knowledge Base Solution

Go to Knowledge Base, enter the keywords of the issue you face to find for the solution.

Supported Flash Memory Devices (Configuration Devices)

Table 3 - FPGA Configuration Devices

Configuration Device FamilyCapacityPackageVoltageFPGA Product Family Compatibility
EPCQ-A†4 Mb - 32 Mb8-pin SOIC3.3 VCompatible with Stratix® V, Arria® V, Cyclone® V, Cyclone® 10 LP and earlier FPGA families.
EPCQ-A†64 Mb - 128 Mb16-pin SOIC3.3 VCompatible with Stratix® V, Arria® V, Cyclone® V, Cyclone® 10 LP and earlier FPGA families.
Notes: † EPCQ-A family is supported from Quartus® Prime Standard Edition Software v17.1 onwards. For product family support for legacy families not included in version 17.1 file a Service Request. See also Configuration Devices.

Supported Third Party Configuration Devices in SDM Devices

The AN 981: Using Generic QSPI Flash on SDM Devices provides guidance on how to select a 3rd party QSPI flash for SDM devices. Beside AN 981, the table below provides recently tested QSPI flash, which matches the flash requirements found in AN 981: Using Generic QSPI Flash on SDM Devices. 

Their status is as follows:

  • Altera Tested and Supported: These devices receive regression testing with FPGA tools, and their use is fully supported by Altera FPGA Technical Support.
  • Known to Work: These devices receive preliminary sanity testing with FPGA tools. They are not readily found in the Programming File Generator – Configuration Device list, thus need to be manually defined through the New Flash Memory Configuration Device. 

Note: All flashes are tested with the highest AS_CLK frequency possible, after considering both the "AC Characteristic" and the "Supported Clock Frequency of each Fast Read Operations" tables for each flash to support 1-1-1 Fast Read and 4-4-4 QPI Read.

For example, if the critical path is 4-4-4 QPI Read at factory settings (with maximum clock frequency of 84MHz), the highest AS_CLK frequency possible is 77MHz with Internal Oscillator. For more information, please refer to AN 981: Using Generic QSPI Flash on SDM Devices - Maximum QSPI Clock.

Table 4 - Supported Third Party Configuration Devices

FPGAVendorPart NumberByte addressingDummy Clock SettingsPermanent Quad-Enabled flash?Support Category
 PrefixSuffix ASx1ASx4 
Agilex® 7(8) Agilex® 5 and Agilex® 3MicronMT25QU128ABA8E12-0AAT3-byte(1)N/ANote(5)NoAltera Tested and Supported
MT25QU256ABA8E12-0AAT
MT25QU512ABB8E12-0AAT
MT25QU01GBBB8E12-0AAT
MT25QU02GCBB8E12-0AAT
MacronixMX25U12835FXDI-10G3-byte(1)N/ANote(5)NoAltera Tested and Supported
MX25U25643GXDI00Known to Work(2,4)
MX25U12843GXDI00Known to Work(2,3)
MX25U12845GXDI00
MX25U25645GXDI00Altera Tested and Supported
MX25U51245GXDI00
MX66U1G45GXDI00
MX66U2G45GXRI00
Stratix® 10, Agilex® 7, Agilex® 5 and Agilex® 3 devices do not support Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54.
ISSIIS25WP256E-RHLE3-byte(1)N/ANote(5)NoKnown to Work(2,4)
IS25WP512M-RHLE
IS25WP01G-RHLE(6)
Stratix® 10, Agilex® 7, Agilex® 5, and Agilex® 3 devices do not support ISSI configuration device with part number IS25WP256D-RHLE.
GigadeviceGD25LB512MEBFRY(7)3-byte(1)N/ANote(5)NoKnown to Work(2,3,4)
GD25LT512MEBIRY(7)
GD55LB01GEBIRY(7)
GD55LT01GEBFRY(7)
GD55LB02GEBIR(7)
WinbondW25Q512NWFIA(7)3-byte(1)N/ANote(5)NoKnown to Work(2,4)
W25Q02NWTBIAKnown to Work(2,3)
W25Q01NWTBIA
Stratix® 10MicronMT25QU128ABA8ESF-0SIT3-byte(1)N/ANote(5)NoKnown to Work(2)
MT25QU256ABA8E12-1SIT
MT25QU512ABB8ESF-0SIT
MT25QU01GBBB8ESF-0SITAlteraTested and Supported
MT25QU02GCBB8E12-0SITKnown to Work(2)
MacronixMX25U12835FMI-1003-byte(1)N/ANote(5)NoKnown to Work(2)
MX25U12843GXDI00Known to Work(2,3)
MX25U12845GXDI00
MX25U25643GXDI00Known to Work(2,4)
MX25U25645GXDI00
MX25U51245GXDI00
MX66U51235FXDI-10GKnown to Work(2)
MX66U1G45GXDI00
MX66U2G45GXRI00Altera Tested and Supported
Stratix® 10, Agilex® 7, Agilex® 5 and Agilex® 3 devices do not support Macronix configuration devices with part number MX25U25645GXDI54, MX25U51245GXDI54, MX66U1G45GXDI54 and MX66U2G45GXRI54.
ISSIIS25WP256E-RHLE3-byte(1)N/ANote(5)NoKnown to Work(2,4)
IS25WP512M-RHLE
IS25WP01G-RILE(6)
Stratix® 10, Agilex® 7, Agilex® 5 and Agilex® 3 devices do not support ISSI configuration device with part number IS25WP256D-RHLE.
GigadeviceGD25LB512MEBFRY(7)3-byte(1)N/ANote(5)NoKnown to Work(2,3,4)
GD25LT512MEBIRY(7)
GD55LB01GEBIRY(7)
GD55LT01GEBFRY(7)
GD55LB02GEBIR(7)
WinbondW25Q512NWFIA(7)3-byte(1)N/ANote(5)No(6)Known to Work(2,4)
W25Q02NWTBIAKnown to Work(2)
W25Q01NWTBIA

Notes:

  1. Using the default setting of the configuration devices.
  2. Tested with FPGA Active Serial Configuration
  3. Tested with Remote System Update (RSU)
  4. Tested with boot HPS from QSPI
  5. FPGA boot ROM perform normal READ operation to load the firmware which is initial part of the bit stream, after firmware is loaded, it reads the Serial Flash Discovery Parameter(SFDP) table defined by flash vendor to determine the number of dummy clock cycles for performing Quad I/O FAST READ operation to load the rest of the bit stream.
  6. You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x9d 0x70 0x1b, Device density=1024Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Quartus Prime Pro Edition.
  7. You need to define New Flash Memory Configuration Device based on programming flow template: Device ID=0x00 0x00 0x00, Device density=512Mb/1024Mb/2048Mb, Total device die=1, Programming flow template=Macronix. Refer to add a custom flash device in Generic Flash Programmer User Guide: Quartus Prime Pro Edition.
  8. In Agilex® 7 F & I-Series devices, when the SDM runs the boot ROM firmware, it takes about 800ns to reset the flash memory using the AS_nRST reset pin before reading from the flash memory. This may violate the reset timing specification from QSPI flash memory vendors Macronix, Winbond and ISSI. Due to this, the SDM may fail to read the flash memory and may get stalled at the boot ROM phase. To workaround this problem, toggle the nCONFIG to recover from this issue and reconfigure the device.

Supported Third Party Configuration Devices in Control-Block based Devices

The AN 1013: Using Generic QSPI Flash on Control Block-Based Devices provides more information on how to select a 3rd party QSPI flash for control block-based devices. Besides AN1013, the table below provides recently tested QSPI flash, which matches the flash requirements found in AN 1013: Using Generic QSPI Flash on Control Block-Based Devices.

Their status is as follows:

  • Altera Tested and Supported: These devices receive regression testing with FPGA tools, and their use is fully supported by Altera FPGA Technical Support.
  • Known to Work: These devices receive preliminary sanity testing with FPGA tools. They are not readily found in the Convert Programming File – Configuration Device list, thus need to be manually defined through the New Flash Memory Configuration Device. 

Note: All flashes are tested with the highest DCLK frequency possible, after considering both the "AC Characteristic" and the "Supported Clock Frequency of each Fast Read Operations" tables for each flash to support 1-1-1 Fast Read and 1-4-4 Quad IO Read.

For example, if the critical path is 1-4-4 Quad IO Read at factory settings (with maximum clock frequency of 84MHz), the highest AS_CLK frequency possible with Internal Oscillator should be lower than 84MHz. For more information, please refer to AN 1013: Using Generic QSPI Flash on Control Block-Based Devices - Maximum QSPI Clock Frequency.

Table 5 - Supported Third Party Configuration Devices

FPGAVendorPart NumberByte addressingDummy Clock SettingsPermanent Quad-Enabled flash?Support Category
 PrefixSuffix ASx1ASx4 

Arria® 10

Cyclone® 10 GX

MicronMT25QU256ABA8E12-1SIT4-byte(3)10(3)10(3)No(4)Known to Work(5)
MT25QU512ABB8ESF-0SITKnown to Work(5,7)
MT25QU512ABB8E12-0SITKnown to Work(7)
MT25QL512ABA8ESF-0SIT
MT25QL512ABB8ESF-0SIT
MT25QU01GBBB8ESF-0SITKnown to Work(5,7)
MT25QU01GBBB8E12-0SITKnown to Work(7)
MT25QU01GBBA8E12-0SIT
MT25QU02GCBB8E12-0SITKnown to Work(5,7)
MacronixMX25U25645GXDI544-byte(1)10(1)10(1)Yes(1)Known to Work(5)
MX25U51245GXDI54
MX25U51245GMI00(11)3-byte(1)8(1)6(1)No(4)Known to Work(7)
MX66L51235FMI-10G(12)
MX66U1G45GXDI544-byte(1)10(1)10(1)Yes(1)Known to Work(5)
MX66L1G45GMI-10G(13)3-byte(1)8(1)6(1)No(4)Known to Work(7)
MX66U2G45GXRI544-byte(1)10(1)10(1)Yes(1)Known to Work(5)
Cypress/InfineonS25FS512SDSBHV2103-byte(1)(2)8(1)6(1)No(4)Known to Work(7)
S25FL512(14)AGMFI011
S70FL01G(14)SAGMFI011

Stratix® V

Arria® V

Arria® V SoC

Cyclone® V

Cyclone® V SoC

 

MicronMT25QL128ABA8ESF-0SIT3-byte(1)12(3)12(3)No(4)Known to Work(5,7)
MT25QU128ABA8ESF-0SIT3-byte(1)10(1)10(1)No(4)Known to Work(7)
MT25QU256ABA8ESF-0SIT
MT25QL256ABA8ESF-0SIT4-byte(3)4(3)10(3)No(4)Known to Work(5,7)
MT25QL512ABB8ESF-0SIT
MT25QL512ABA8ESF-0SIT3-byte(1)10(1)10(1)No(4)Known to Work(7)
MT25QL01GBBB8ESF-0SIT4-byte(3)4(3)10(3)No(4)Known to Work(5,7)
MT25QL02GCBB8E12-0SITKnown to Work(5)
MacronixMX25L12833FMI-10G(8)3-byte(1)(2)8(1)6(1)No(4)Known to Work(5,7)
MX25L25645GMI-08G(9)
MX25L25635FMI-10G(9)Known to Work(7)
MX25L51245GMI-08G(8)Known to Work(5,7)
MX66L51235FMI-10G(8)Known to Work(7)
MX25U51245GMI00(9)
MX25U51245GXDI00(9)
MX66L1G45GMI-10G(9)
MX66U2G45GXR100(8)
Cypress/InfineonS25FL128(14)SAGMFI0003-byte(1)(2)8(1)6(1)No(4)Known to Work(5,7)
S25FL256(14)SAGMFI000
S25FL512(14)SAGMFI010
S25FL512(14)SAGMFIG11Known to Work(7)
S70FL01G(14)SAGMFI011(10)
GigadeviceGD25Q127CFIG(8)3-byte(1)(2)8(1)4(1)No(4)Known to Work(5,7)
GD25Q256DFIG(8)
Cyclone® 10 LPMicronMT25QL128ABA8ESF-0SIT3-byte(1)(2)8(1)N/ANo(4)Known to Work(5)
MT25QL256ABA8ESF-0SIT
MT25QL512ABB8ESF-0SIT
MT25QL01GBBB8ESF-0SIT
MT25QL02GCBB8E12-0SIT
MacronixMX25L12833FMI-10G3-byte(1)(2)8(1)N/ANo(4)Known to Work(5)
MX25L25645GMI-08G
MX25L51245GMI-08G
Cypress/InfineonS25FL128(14)SAGMFI0003-byte(1)(2)8(1)N/ANo(4)Known to Work(5)
S25FL256(14)SAGMFI000
S25FL512(14)SAGMFI0I0

Notes:

  1. Using the default setting of the configuration devices.
  2. When performing remote system upgrade, the start address of the images must be set within first 128 Mb.
  3. Quartus Programmer set the non-volatile configuration register during programming operation. User need to set the register manually if using a third-party programmer.
  4. Quartus Programmer issues command to enable quad mode
  5. Tested with FPGA Active Serial Configuration
  6. Tested with Remote System Update (RSU)
  7. Tested with boot HPS from QSPI
  8. U-Boot updates needed. U-Boot used for flashing.
  9. U-Boot updates needed.
  10. Two chip selects. HPS Flash Programmer and BootROM use only CS0.
  11. U-Boot modifications needed
  12. Programmed with U-Boot
  13. Programmed with modified U-Boot
  14. The Quartus Prime software does not support the flash specification 'CS# toggle with no CLK and Data is considered as non-valid,' which affects certain configuration devices within the S25FL-S family and S70FL01GS.

Design Examples and Reference Designs

Design Store
 

Agilex® 7 Devices
 

  • Agilex® 7 Mailbox Client FPGA IP Core Design Example (QSPI flash Access and Remote System Update)
     
  • Chip ID Reading using AVST Mailbox IP in Agilex® 7
  • Agilex® 7 P-tile CvP Example Design for Initialization mode

Stratix® 10 Devices

  • Stratix® 10 Mailbox Client FPGA IP Core Design Example (QSPI flash Access and Remote System Update)
     
  • Stratix® 10 CvP Initialization Design Example
  • Stratix® 10 H-Tile CvP Design Example
  • Stratix® 10 H-tile CvP Example Design for Initialization mode
  • Stratix® 10 H-tile CvP Example Design for Update mode
  • Stratix® 10 Serial Flash Mailbox Client FPGA IP Core Design Example

Arria® 10 Devices

  • CvP Example Designs for Arria® 10 GX FPGA Development Kit (FPGA Wiki)
     
  • Arria® 10 Remote System Update (RSU) with Avalon-MM Interface (FPGA Wiki)
  • Board Update Portal Utilizing EPCQ Flash Memory Reference Design
  • Customizable Flash Programmer for Arria® 10
     

Cyclone® 10 GX Devices

  • Cyclone® 10 GX CvP Initialization Design Example
     
  • Cyclone® 10 GX Remote System Update

Cyclone® 10 LP Devices

  • Remote System Upgrade with System Console for Cyclone® 10 LP
     
  • Cyclone® 10 LP Remote System Update Design Example

Table 5 - Training Courses and Videos

FPGA Technical Training Catalog Right arrow
Video TitleDescription
Introduction to Configuring FPGAsLearn the configuration schemes, solutions, features and tools available for configuring FPGAs and programming configuration devices.
Configuration Schemes for FPGAsLearn the difference between all the configuration schemes that can be used to configure FPGAs.
Configuration for Stratix® 10 DevicesLearn the unique configuration features available in the Stratix® 10 devices.
Remote System Upgrade in MAX® 10 DevicesLearn how to set up and perform a RSU in an MAX® 10 device.
Creating Second Stage Bootloader for FPGA SoCsLearn the flow and tools available to quickly customize and generate the second stage boot software.
Mitigating Single Event Upsets in Arria® 10 and Cyclone® 10 GX DevicesLearn the features of the Arria® 10 and Cyclone® 10 GX device families that can be used in the designing your own SEU mitigation solution.
SEU Mitigation in FPGA Devices: Hierarchy TaggingLearn how you can improve your sensitivity processing solution by supplementing single event upset (SEU) mitigation technique with feature called hierarchy tagging.
SEU Mitigation in FPGA Devices: Fault InjectionLearn about Fault Injection IP core and Fault Injection Debugger software to reduce Failure in Time (FIT) rate.
Using the Generic Serial Flash InterfaceLearn how to use the Generic Serial Flash Interface FPGA IP Core to program any serial peripheral interface (SPI) type flash device.
Partial Reconfiguration for FPGA Devices: Introduction & Project AssignmentsPartial Reconfiguration Training part 1 of 4. This part of the training introduces you to the PR feature and the general design flow for a PR design. You'll also learn about design partition and Logic Lock region assignments, required assignments for implementing a PR design, and recommendations for how to floorplan a design for PR.
Partial Reconfiguration for FPGA Devices: Design Guidelines & Host RequirementsPartial Reconfiguration Training part 2 of 4. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations.
Partial Reconfiguration for FPGA Devices: PR Host IP & ImplementationsPartial Reconfiguration Training part 3 of 4. This part of the training discusses all of the PR IP included in the Quartus Prime software, including the PR Controller IP, Region Controller IP, and Freeze Bridge IP. You'll also see how to use these IP to implement either an internal or external host design.
Partial Reconfiguration for FPGA Devices: Output Files & DemonstrationPartial Reconfiguration Training part 4 of 4. This final part of the training discusses the entire design flow for a PR project. It also looks at the files output from the flow. Also included is a demonstration of a complete and functional PR design using the Arria® 10 GX development kit.

Table 6 - Additional Videos

FPGA Quick Videos Right arrow
Video TitleDescription
Implementing a Partial Reconfiguration Design within Qsys for FPGAsWatch this video to learn how to implement Partial Reconfiguration Design within Qsys for FPGAs.
Arria® 10 Configuration via Protocol (CvP)Watch this video to learn how to configure your Arria® 10 device using the PCIe protocol.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part1Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Customize JAM File for Multiple JTAG Devices in a Single JTAG Chain Part2Watch this video to learn about customizing JAM files for a board with multi-device JTAG chains.
How to Perform Active Serial (AS) Configuration via JTAG Interface Using Serial Flash Loader IP CoreWatch this video to learn about configuration schemes other than the usual JTAG configuration. Additionally, this video covers the serial flash loader (SFL) IP core.

For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.

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