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Design optimization can help you improve performance to reduce resource usage, close timing, and reduce compilation times. Support resources for design optimization, physical synthesis, and Design Space Explorer (DSE).
Quartus® Prime software includes a wide range of features to help you optimize your design for area and timing.
- Physical synthesis netlist optimization to optimize designs further than the standard compilation process. Physical synthesis helps improve the performance of your design, regardless of the synthesis tool used.
- DSE automates the search for the settings that give the best results in any individual design. DSE explores the design space of your design, applies various optimization techniques, and analyzes the results to help you discover the best settings for your design.
- The incremental optimization capability in the Quartus® Prime Design Software Pro Edition software offers a fast methodology to converge to design sign-off.
Table 1. Optimization Support Documentation
| User Guide Title | Chapter | Description |
|---|---|---|
| Quartus® Prime Pro Edition User Guides | Area Optimization | This chapter describes techniques to reduce resource usage when designing for Altera® devices. |
| Timing Closure and Optimization | This chapter describes techniques to improve timing performance when designing for FPGA devices. | |
| Analyzing and Optimizing the Design Floorplan | Determining the layout (placement) of your design elements into physical resources on the FPGA device is known as floorplanning. | |
| Chip Planner GUI | The Chip Planner GUI helps you to visualize and modify the use of device resources for your design. As you zoom in, the level of abstraction decreases, revealing more details about your design. | |
| Netlist Optimizations and Physical Synthesis | The Quartus® Prime software offers netlist optimizations during synthesis, and physical synthesis optimization during fitting, that can improve the performance of your design. |
Table 2. Optimization Support Resources
| Resource Centers | Description |
|---|---|
| Synthesis and Netlist Viewer | Following recommended coding guidelines can be a powerful way to obtain good quality results. Refer to the Design and Coding Guidelines section in the Synthesis and Netlist Viewer Resource Center for more information. |
| Incremental Compilation | You can use incremental compilation to reduce compilation times and preserve results during optimization. |
Table 3. Optimization Support Training Courses and Demonstrations
| Course Title | Course Description |
|---|---|
| External Memory Interfaces in Agilex® FPGAs (Part 4): On-Chip Debugging | This training is part 4 of 4. Agilex® FPGAs introduce a brand new, higher performance architecture for implementing external memory interfaces, including DDR5 running at up to 5.6 Gbps on some devices. |
| Using Quartus® Prime Pro Software: Chip Planner | This training will introduce you to the Chip Planner tool that is a part of the Quartus® Prime Pro software. You will learn how to analyze your design using the Chip Planner features such as chip resource views, critical path analysis and routing congestion analysis. You will learn how to go about floorplanning your design with Logic Logic regions. Finally, you will learn to use the Resource Property Editor to look at fine details of your design. |
| Using Design Space Explorer | Learn how to use the Quartus® Prime Pro Design Space Explorer II (DSE) as an aid to remote and parallel compilation. |
| Best Design Practices for Timing Closure | Learn how to address timing closure issues with HDL design techniques. |