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Arria® V GX FPGA
Offers the lowest total power for mid-range applications and the lowest power transceivers for speeds up to 10.3125 Gbps.
Explore the Arria® V GX FPGA
Arria V GX and GT FPGA offers the lowest total power for mid-range applications by using the 28 nm low power process to deliver the lowest static power, offering the lowest power transceivers for speeds up to 10.3125 Gbps, and providing superior fabric with hard IP designed to lower dynamic power.
Key Features
| Multi-Protocol Serial Connectivity | Supports a wide range of serial protocols and data rates for applications in video processing, communications, and industrial automation. |
| Efficient Signal Processing | Includes rich DSP resources and embedded memory to accelerate complex signal processing tasks in real-time systems. |
| Flexible Logic Integration | Offers balanced logic, memory, and transceiver resources to support diverse embedded applications with scalable performance. |
Benefits
Versatile Multi-Protocol Connectivity
Combines moderate logic density with high-speed transceivers, supporting multi-protocol serial connectivity for applications like broadcast, video processing, and industrial automation.
Efficient Signal Processing Acceleration
Provides a flexible mix of logic, DSP blocks, and embedded memory, enabling efficient acceleration of complex signal processing and control algorithms.
Power-Optimized Embedded Applications
Optimized for power-sensitive designs that require reliable serial communication, while maintaining flexibility for a variety of mid-range embedded applications.
Product Package & Combination Selector
Start Design
Start your Arria V GX FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
Multi-Rate Ethernet PHY FPGA IP
This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.
CIC FPGA IP Core
CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample-rate-conversion designs, such as digital down converters (DDC) and digital up converters (DUC).
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Solutions
Arria® V GX FPGAs for Industrial
Arria® V GX FPGAs for Medical
Arria® V GX FPGAs for Consumer Electronics
Resources
Documentation, downloads, videos, training, and support for Cyclone V ST FPGA
Common Questions
The device overview specifies GX transceivers up to 6.5536 Gbps. Confirm speed-grade and channel conditions in the datasheet.
Choose GX when its bandwidth and resources meet requirements. Evaluate GZ when documented higher serial rates or architecture differences are needed.
Use buffers and explicit flow control, then calculate worst-case occupancy and sustained throughput for the expected traffic.
Check device support, physical rate, interface features and release compatibility. An IP catalog listing does not guarantee the desired configuration.
Test transport with known patterns first, then compare processing outputs with a numerical reference using controlled input data.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.