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Arria® V SX FPGA
Altera SoC FPGA with ARM*-based HPS and 6.5536 Gbps backplane-capable transceivers.
Explore the Arria® V SX FPGA
SoC FPGA with ARM*-based HPS and 10.3125 Gbps transceivers.
Key Features
| Integrated ARM Processing | Combines programmable logic with dual-core ARM® Cortex®-A9 processors for hardware-software co-design in embedded applications. |
| Simplified System Integration | Consolidates processing, logic, and I/O interfaces into a single device to reduce board complexity and design time. |
| Flexible Embedded Control | Enables system designers to efficiently manage control, signal processing, and data movement in a wide range of embedded systems. |
Benefits
Unified Processing and Logic Platform
Integrates dual-core ARM® processors with FPGA fabric to provide a flexible platform for real-time processing and hardware acceleration.
Consolidated Control and Data Processing
Supports the integration of control-plane and data-plane functions for streamlined embedded system designs.
Power-Efficient Embedded Solutions
Delivers processing and programmability with optimized power efficiency for industrial, medical, and automotive applications.
Product Package & Combination Selector
Start Design
Start your Arria V SX FPGA design — choose a design phase below to jump to the right tools, guides, and resources.
Multi-Rate Ethernet PHY FPGA IP
This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.
Nios® V Processors
By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production.
Solutions
Arria® V SX FPGAs for Industrial
Arria® V SX FPGAs for Medical
Arria® V SX FPGAs for Customer Electronics
Resources
Documentation, downloads, videos, training, and support for Cyclone V ST FPGA
Common Questions
Choose ST when its documented higher transceiver rate is required. Compare selected-part resources and interface support separately.
Use supported bridges and memory-mapped control registers with a matching driver and address map. Keep bulk traffic on an appropriate data path.
Software manages configuration and policy. FPGA logic performs the configured parallel data processing at the required throughput.
Check bridge enablement, fabric configuration, addresses, clocks and reset state. Isolate a simple known register before testing the full pipeline.
Use DMA for bulk transfers when supported by the design. Define buffer ownership, memory ordering and any required cache maintenance.
Ready to Order?
Ordering starts with a part number. Select a product in the table above to view its ordering part numbers (OPNs) — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.