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Cyclone® V E
Cyclone® V E FPGAs are optimized for low system cost and power for a wide spectrum of general logic and DSP applications.
Explore the Cyclone® V E FPGA
Cyclone® V E FPGAs are the general-logic members of the Cyclone V family, built on TSMC's 28-nm low-power (28LP) process. The E-Series spans five devices from 25K to 301K logic elements, with up to 12,200 Kb of M10K embedded memory, 342 variable-precision digital signal processing (DSP) blocks, 480 general-purpose I/Os, and two hard memory controllers. With no transceivers and no hard processor system, Cyclone V E FPGAs delivers the lowest system cost and power in the family for general logic and DSP designs.
Key Features
| Internal memory blocks | M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC). Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory. |
| General-purpose I/Os | 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter. 400 MHz/800 Mbps external memory interface. On-chip termination (OCT). 3.3 V support with up to 16 mA drive strength. |
| Variable-precision DSP blocks | Variable-precision DSP: Native support for up to three signal processing precision levels in the same variable-precision DSP block, 64-bit accumulator, and cascade. |
| Embedded hard IP blocks | Support up to two hard memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with two chip selects and optional ECC. |
Benefits
Do More with Less Power, Design Time, and Cost
Built on TSMC's 28LP process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more.
Logic Integration and Differentiation Capabilities
It offers an 8-input adaptive logic module (ALM) and variable-precision DSP blocks, allowing up to 13.59 megabits (Mb) of embedded memory.
Lower System Cost
Operating requires only two core voltages and is available in low-cost wire-bond packaging. Includes innovative features such as Configuration via Protocol (CvP) and partial reconfiguration.
Product Package & Combination Selector
Start Design
Everything you need to begin a Cyclone V E FPGA design.
Embedded Memory IP
On-chip memory resources for fast local data storage.
DSP Block IP
Accelerates complex filtering and signal processing workloads.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Quartus Prime Design Software Standard Edition
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Design Software Lite Edition
A free, entry-level FPGA design solution that provides basic compilation, programming, and debugging capabilities for select device families.
Solutions
Cyclone V E FPGAs for Industrial
Cyclone V E FPGAs for Consumer Electronics
Cyclone V E FPGAs for Medical
Resources
Start developing with Cyclone V E FPGAs with these resources.
Training & Learning
Common Questions
Choose E when general logic, DSP, and parallel interfaces meet requirements. Choose GX when its hard serial-transceiver resources are needed.
Compare the algorithm's error tolerance with supported arithmetic modes, then verify numeric accuracy and resource mapping.
Choose according to depth, width, ports and placement. Inspect implementation results because the most efficient choice depends on the access pattern.
Check supported memory settings, pins, clocks, resets, and PCB integrity using the corresponding EMIF documentation and debug flow.
Check whether the claimed flow requires PCIe* resources absent from the selected E device. Use that device's documented configuration modes.