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Cyclone® V SE
The Cyclone® V SE FPGA is optimized for low system cost and power with an integrated Arm Cortex*-A9 MPCore processor system for general logic and DSP applications.
Explore the Cyclone® V SE SoC FPGA
Cyclone® V SE SoC FPGAs pair the Cyclone V FPGA fabric with a hard processor system (HPS) built around a dual-core Arm Cortex*-A9 MPCore processor, on TSMC's 28-nm low-power process. The SE series spans four devices from 25K to 110K logic elements, with up to 5,570 Kb of M10K embedded memory, 112 variable-precision digital signal processing (DSP) blocks, and a hard multiport SDRAM controller in the HPS. With no transceivers, the Cyclone V SE SoC is the lowest cost, lowest power entry point to Cyclone V SoC designs.
Key Features
| Embedded Memory Blocks | M10K: 10-kilobits (Kb) memory blocks with soft error correction code (ECC). Memory logic array block (MLAB): 640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory. |
| General-Purpose I/Os | 875 megabits per second (Mbps) low-voltage differential signaling (LVDS) receiver and 840 Mbps LVDS transmitter. 400 MHz/800 Mbps external memory interface. On-chip termination (OCT). 3.3 V support with up to 16 mA drive strength. |
| External Memory Interface | In Cyclone V SoC devices, an additional hard memory controller in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices. |
| HPS | The HPS consists of a dual-core Arm Cortex* -A9 MPCore processor, a rich set of peripherals, and a shared multiport SDRAM memory controller. |
Benefits
Do More with Less Power, Design Time, and Cost
Built on TSMC's 28-nm low-power (28LP) process technology, including an abundance of hard intellectual property (IP) blocks, allowing you to differentiate and do more.
Logic Integration and Differentiation Capabilities
It offers an 8-input adaptive logic module (ALM) and variable-precision DSP blocks, allowing up to 13.59 megabits (Mb) of embedded memory.
Lower System Cost
Operating requires only two core voltages and is available in low-cost wire-bond packaging. Includes innovative features such as partial reconfiguration.
Product Package & Combination Selector
Start Design
Everything you need to begin a Cyclone V SE SoC FPGA design.
Embedded Memory IP
On-chip memory resources for fast local data storage.
Arm Cortex-A9 Processor IP
Provides embedded processing for hardware-software integration.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Quartus Prime Design Software Standard Edition
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Design Software Lite Edition
A free, entry-level FPGA design solution that provides basic compilation, programming, and debugging capabilities for select device families.
Solutions
Cyclone V SE FPGAs for Industrial
Cyclone V SE FPGAs for Consumer Electronics
Cyclone V SE FPGAs for Medical
Resources
Start developing with Cyclone V SE FPGAs with these resources.
Training & Learning
Common Questions
SE has an integrated Arm HPS without hard serial transceivers. SX adds documented serial-transceiver capability.
Choose SE when integrated Arm software is needed alongside custom logic. Choose E when no hard processor is required.
Start from a validated hardware/software reference and boot flow, then add custom peripherals incrementally and verify each interface.
Check interrupt routing, device-tree configuration, driver handling, signal synchronization and the peripheral's interrupt-clear behavior.
Use external SDRAM when OS, application or buffer capacity exceeds on-chip storage. Check HPS memory configuration and traffic demands.