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Product Family
MAX® V
MAX® V CPLDs offer a unique, non-volatile architecture, delivering low power and on-chip features.
Explore the MAX® V Family
The MAX® V family of low-cost, low-power CPLDs offers high density and I/O count per footprint. Ranging from 40 to 2,210 logic elements and up to 271 I/Os, MAX V devices provide programmable solutions for I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog IC interface.
Key Features
| Integrated System Functions | Combines flash memory, RAM, and oscillator functions within the device to simplify system design, reduce external component count, and minimize board complexity. |
| Low Power Operation | Delivers power-efficient performance with low static power and simplified power supply requirements, helping designers extend battery life and optimize power usage in portable and energy-sensitive applications. |
| Non-Volatile Configuration and In-System Programming | Supports embedded flash and in-system programming, enabling flexible device updates and non-volatile storage of system configuration data without disrupting system operation. |
Benefits
Integrated, Low-Cost CPLD
The MAX V architecture integrates functions such as flash, RAM, and oscillators into a single device, reducing system complexity and helping minimize board size and component count.
Lower Total Power
Delivers low static power operation with simplified power supply requirements, helping designers optimize power efficiency and extend battery life in portable and energy-sensitive applications.
Easy to Use
Provides non-volatile memory storage with in-system programming and embedded flash, enabling system updates and configuration flexibility without interrupting system operation.
Start Design
Choose a resource below to start your MAX V CPLD design, from development kit to software downloads.
FFT FPGA IP Cores
The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.
Nios® V Processors
By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Quartus Prime Design Software Standard Edition
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Design Software Lite Edition
A free, entry-level FPGA design solution that provides basic compilation, programming, and debugging capabilities for select device families.
Solutions
MAX V CPLDs for Industrial
MAX V CPLDs for Consumer Electronics
MAX V CPLDs for Security
Resources
Start developing with MAX V CPLDs with these resources.
Training & Learning
Common Questions
MAX V CPLDs target compact nonvolatile control functions. FPGA families provide different resource and processing capabilities; compare the actual implementation needs.
Use MAX V CPLDs when its logic, I/O, and startup behavior satisfy the sequence. Define safe outputs and external fault handling.
Define supported electrical interfaces and control timing, then synthesize and verify resource use. Do not assume a full FPGA protocol core will fit.
Follow the device's documented programming behavior and board-level safety design. Verify actual pin states during interruption and recovery.
Evaluate MAX 10 FPGAs when the design requires additional DSP, memory, or supported analog integration beyond suitable CPLD control functions.